Philips 74LV74PW, 74LV74N, 74LV74DB, 74LV74D Datasheet

INTEGRATED CIRCUITS

74LV74

Dual D-type flip-flop with set and reset; positive-edge trigger

Product specification

1998 Apr 20

Supersedes data of 1996 Nov 07

IC24 Data Handbook

m n r

	Philips Semiconductors	Product specification
	Dual D-type flip-flop with set and reset;	74LV74
	positive edge-trigger

FEATURES

•Wide operating voltage: 1.0 to 5.5V

•Optimized for Low Voltage applications: 1.0 to 3.6V

•Accepts TTL input levels between VCC = 2.7V and VCC = 3.6V

•Typical VOLP (output ground bounce) 0.8V @ VCC = 3.3V, Tamb = 25°C

•Typical VOHV (output VOH undershoot) 2V @ VCC = 3.3V, Tamb = 25°C

•Output capability: standard

•ICC category: flip-flops

DESCRIPTION

The 74LV74 is a low-voltage Si-gate CMOS device and is pin and function compatible with 74HC/HCT74.

The 74LV74 is a dual positive edge triggered, D-type flip-flop with individual data (D) inputs, clock (CP) inputs, set (SD) and (RD)

inputs; also complementary Q and Q outputs.

The set and reset are asynchronous active LOW inputs and operate independently of the clock input. Information on the data input is transferred to the Q output on the LOW-to-HIGH transition of the clock pulse. The D inputs must be stable one set-up time prior to the LOW-to-HIGH clock transition, for predictable operation.

Schmitt-trigger action in the clock input makes the circuit highly tolerant to slower clock rise and fall times.

QUICK REFERENCE DATA

GND = 0V; Tamb = 25°C; tr =tf 2.5 ns

	SYMBOL						PARAMETER	CONDITIONS	TYPICAL	UNIT
		Propagation delay						CL = 15pF	11
		nCP to nQ, nQ
	tPHL/tPLH							VCC = 3.3V	14	ns
		nS		D to nQ, nQ
									14
		nR		D to nQ, nQ
	fmax	Maximum clock frequency						CL = 15pF	76	MHz
								VCC = 3.3V
	CI	Input capacitance							3.5	pF
	CPD	Power dissipation capacitance per flip-flop						Notes 1 and 2	24	pF

NOTES:

1.CPD is used to determine the dynamic power dissipation (PD in μW) PD = CPD VCC2 x fi (CL VCC2 fo) where:

fi = input frequency in MHz; CL = output load capacitance in pF;

fo = output frequency in MHz; VCC = supply voltage in V;

(CL VCC2 fo) = sum of the outputs.

2.The condition is VI = GND to VCC

ORDERING INFORMATION

PACKAGES	TEMPERATURE RANGE	OUTSIDE NORTH AMERICA	NORTH AMERICA	PKG. DWG. #
14-Pin Plastic DIL	±40°C to +125°C	74LV74 N	74LV74 N	SOT27-1
14-Pin Plastic SO	±40°C to +125°C	74LV74 D	74LV74 D	SOT108-1
14-Pin Plastic SSOP Type II	±40°C to +125°C	74LV74 DB	74LV74 DB	SOT337-1
14-Pin Plastic TSSOP Type I	±40°C to +125°C	74LV74 PW	74LV74PW DH	SOT402-1

PIN DESCRIPTION

	PIN	SYMBOL							FUNCTION
	NUMBER
									Asynchronous reset-direct input
	1, 13	1RD, 2RD
									(active-LOW)
	2, 12	1D, 2D							Data inputs
	3, 11	1CP, 2CP							Clock input (LOW-to-HIGH),
									edge-triggered)
									Asynchronous set-direct input
	4, 10	1SD, 2SD
									(active-LOW)
	5, 9	1Q, 2Q							True flip-flop outputs
	6, 8								Complement flip-flop outputs
		1Q				, 2Q
	7		GND						Ground (0V)
	14			VCC					Positive supply voltage

FUNCTION TABLE

INPUTS

OUTPUTS

D

D

CP

D

Q

S

R

Q

L

H

X

X

H

L

H

L

X

X

L

H

L

L

X

X

H

H

INPUTS

OUTPUTS

S

D

R

D

CP

D

Qn+1

Q

n+1

H

H

L

L

H

H

H

H

H

L

H

=

HIGH voltage level

L

=

LOW voltage level

X

=

don't care

= LOW-to-HIGH CP transition

Qn+1 = state after the next LOW-to-HIGH CP transition

1998 Apr 20

2

853-1888 19258

Philips Semiconductors	Product specification

Dual D-type flip-flop with set and reset;

74LV74

positive edge-trigger

PIN CONFIGURATION

LOGIC SYMBOL

VCC

1RD

1

14

4

10

1D

2

13

2RD

1S

D

2SD

1CP

3

12

2D

2

1D

SD

1Q

5

D

Q

12

2D

2Q

9

1SD

4

11

2CP

3

1CP

CP

FF

11

2CP

6

1Q

1Q

5

10

2SD

Q

RD

2Q

8

1Q

6

9

2Q

GND

1RD

2RD

7

8

2Q

1

13

SV00330

SV00331

LOGIC SYMBOL (IEEE/IEC)

FUNCTIONAL DIAGRAM

4

S

5

3

C1

4

1SD

2

1D

SD

1Q

5

2

1D

6

3

1CP

D

Q

1

R

CP

FF1

1Q

6

10

Q

RD

S

9

11

C2

1

1R

D

12

D

2D

8

10

2S

13

R

12

2D

SD

2Q

9

SV00332

11

2CP

D

Q

CP

FF2

8

2Q

Q

RD

13

2R

D

SV00333

1998 Apr 20

3

Philips Semiconductors	Product specification

Dual D-type flip-flop with set and reset;

74LV74

positive edge-trigger

LOGIC DIAGRAM (ONE FLIP-FLOP)

			Q
	C		C
	C	C
	C		C
D
			Q
	C	C
RD
SD
CP	C
	C
			SV00334

RECOMMENDED OPERATING CONDITIONS

SYMBOL	PARAMETER	CONDITIONS	MIN	TYP.	MAX	UNIT
VCC	DC supply voltage	See Note1	1.0	3.3	5.5	V
VI	Input voltage		0	±	VCC	V
VO	Output voltage		0	±	VCC	V
Tamb	Operating ambient temperature range in free	See DC and AC	±40		+85	°C
	air	characteristics	±40		+125
		VCC = 1.0V to 2.0V	±	±	500
tr, tf	Input rise and fall times except for	VCC = 2.0V to 2.7V	±	±	200	ns/V
	Schmitt-trigger inputs	VCC = 2.7V to 3.6V	±	±	100
		VCC = 3.6V to 5.5V	±	±	50

NOTE:

1. The LV is guaranteed to function down to VCC = 1.0V (input levels GND or VCC); DC characteristics are guaranteed from VCC = 1.2V to VCC = 5.5V.

ABSOLUTE MAXIMUM RATINGS1, 2

In accordance with the Absolute Maximum Rating System (IEC 134)

Voltages are referenced to GND (ground = 0V)

	SYMBOL	PARAMETER	CONDITIONS	RATING	UNIT
	VCC	DC supply voltage		±0.5 to +7.0	V
	±IIK	DC input diode current	VI < ±0.5 or VI > VCC + 0.5V	20	mA
	±IOK	DC output diode current	VO < ±0.5 or VO > VCC + 0.5V	50	mA
	±IO	DC output source or sink current	±0.5V < VO < VCC + 0.5V		mA
		± standard outputs		25
	±IGND,	DC VCC or GND current for types with			mA
		±standard outputs		50
	±ICC
	Tstg	Storage temperature range		±65 to +150	°C
		Power dissipation per package	for temperature range: ±40 to +125°C
	Ptot	±plastic DIL	above +70°C derate linearly with 12mW/K	750	mW
		±plastic mini-pack (SO)	above +70°C derate linearly with 8 mW/K	500
		±plastic shrink mini-pack (SSOP and TSSOP)	above +60°C derate linearly with 5.5 mW/K	400

NOTES:

1.Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under ªrecommended operating conditionsº is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

2.The input and output voltage ratings may be exceeded if the input and output current ratings are observed.

1998 Apr 20

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