Philips 74LV595PW, 74LV595N, 74LV595DB, 74LV595D Datasheet

INTEGRATED CIRCUITS

74LV595

8-bit serial-in/serial or parallel-out shift register with output latches (3-State)

Product specification

1998 Apr 20

IC24 Data Handbook

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	Philips Semiconductors	Product specification
	8-bit serial-in/serial or parallel-out shift register	74LV595
	with output latches (3-State)

FEATURES

•Optimized for Low Voltage applications: 1.0V to 3.6V

•Accepts TTL input levels between VCC = 2.7V and VCC = 3.6V

•Typical VOLP (output ground bounce) < 0.8V at VCC = 3.3V, Tamb = 25°C

•Typical VOHV (output VOH undershoot) > 2V at VCC = 3.3V,

Tamb = 25°C

•8-bit serial input

•8-bit serial or parallel output

•Storage register with 3-State outputs

•Shift register with direct clear

•Output capability:

±parallel outputs; bus driver

±serial output; standard

•ICC category: MSI

APPLICATIONS

•Serial-to-parallel data conversion

•Remote control holding register

DESCRIPTION

The 74LV595 is a low-voltage Si-gate CMOS device that is pin and function compatible with 74HC/HCT595.

The74LV595 is an 8-stage serial shift register with a storage register and 3-State outputs. The shift register and storage register have separate clocks.

Data is shifted on the positive-going transitions of the SHCP input. The data in each register is transferred to the storage register on a positive-going transition of the STCP input. If both clocks are connected together, the shift register will always be one clock pulse ahead of the storage register.

The shift register has a serial input (DS) and a serial standard output (Q7') all for cascading. It is also provided with asynchronous reset

(active LOW) for all 8 shift register stages. The storage register has 8 parallel 3-State bus driver outputs. Data in the storage register appears at the output whenever the output enable input (OE) is LOW.

QUICK REFERENCE DATA

GND = 0V; Tamb = 25°C; tr =tf 2.5 ns

SYMBOL			PARAMETER	CONDITIONS	TYPICAL	UNIT
		Propagation delay		CL = 15pF
tPHL/tPLH		SHCP to Q7'		VCC= 3.3V	15	ns
		STCP to Q7'			16
		MR	to Q7'		14
fmax		Maximum clock frequency SHCP, STCP			77	MHz
CI		Input capacitance			3.5	pF
CPD		Power dissipation capacitance per gate		VCC = 3.3V	115	pF
				Notes 1 and 2

NOTES:

1.CPD is used to determine the dynamic power dissipation (PD in μW)

PD = CPD VCC2 x fi (CL VCC2 fo) where:

fi = input frequency in MHz; CL = output load capacitance in pF;

fo = output frequency in MHz; VCC = supply voltage in V;

(CL VCC2 fo) = sum of the outputs.

2.The condition is VI = GND to VCC.

ORDERING AND PACKAGE INFORMATION

PACKAGES	TEMPERATURE RANGE	OUTSIDE NORTH AMERICA	NORTH AMERICA	PKG. DWG. #
16-Pin Plastic DIL	±40°C to +125°C	74LV595 N	74LV595 N	SOT38-4
16-Pin Plastic SO	±40°C to +125°C	74LV595 D	74LV595 D	SOT109-1
16-Pin Plastic SSOP Type II	±40°C to +125°C	74LV595 DB	74LV595 DB	SOT338-1
16-Pin Plastic TSSOP Type I	±40°C to +125°C	74LV595 PW	74LV595PW DH	SOT403-1

1998 Apr 20

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853-1987 19255

Philips Semiconductors	Product specification

8-bit serial-in/serial or parallel-out shift register

74LV595

with output latches (3-State)

PIN DESCRIPTION

	PIN	SYMBOL				FUNCTION
	NUMBER
	15, 1, 2, 3,	Q0 to Q7				Parallel data output
	4, 5, 6, 7
	8	GND				Ground (0V)
	9		Q7'			Serial data output
	10					Master reset (active LOW)
			MR
	11	SHCP				Shift register clock input
	12	STCP				Storage register clock input
	13					Output enable input (active LOW)
			OE
	14		DS			Serial data input
	16	VCC				Positive supply voltage

PIN CONFIGURATION

Q1
	1		16		VCC
Q2
					Q0
	2		15
					DS
Q3	3		14
Q4	4		13		OE
Q5	5		12		STCP
					SHCP
Q6	6		11
Q7	7		10		MR
					Q7'
GND	8		9
		SV00720

FUNCTION TABLE

INPUTS

OUTPUTS

FUNCTION

SHCP

STCP

DS

Q7'

Qn

OE

MR

X

X

L

L

X

L

NC

A LOW level on

only affects the shift registers

MR

X

°

L

L

X

L

L

Empty shift register loaded into storage register

X

X

H

L

X

L

Z

Shift register clear. Parallel outputs in high-impedance OFF-states

Logic high level shifted into shift register stage 0. Contents of all shift

°

X

L

H

H

Q6'

NC

register stages shifted through, e.g. previous state of stage 6 (internal

Q6') appears on the serial output (Q7')

X

°

L

H

X

NC

Qn'

Contents of shift register stages (internal Qn') are transferred to the

storage register and parallel output stages

Contents of shift register shifted through. Previous contents of the shift

°

°

L

H

X

Q6'

Qn'

register are transferred to the storage register and the parallel output

stages

H

= HIGH voltage level

L

= LOW voltage level

X

= Don't care

Z = High impedance OFF-state NC= No change

° = LOW-to-HIGH clock transition

↓ = HIGH-to-LOW transition

1998 Apr 20

3

Philips Semiconductors	Product specification

8-bit serial-in/serial or parallel-out shift register

74LV595

with output latches (3-State)

LOGIC SYMBOL

FUNCTIONAL DIAGRAM

		11				12
		SHCP				STCP
								Q7'				9
								Q0				15
								Q1				1
								Q2				2
14		DS						Q3				3
												4
								Q4
								Q5				5
								Q6				6
								Q7				7
			MR				OE
		10				13				SV00723

DS
14
SHCP		8±STAGE SHIFT
11			REGISTER
MR
10
							Q7'
							9
STCP		8±BIT STORAGE
12			REGISTER
OE		3±STATE OUTPUTS
13
Q0	Q1	Q2	Q3	Q4	Q5	Q6	Q7
15	1	2	3	4	5	6	7
							SV00725

LOGIC SYMBOL (IEEE/IEC)

	13		EN3
	12		C2
	10	R	SRG8
	11		C1/
	14	1D		15
			2D	3
				1
				2
				3
				4
				5
				6
				7
				9
				SV00724

1998 Apr 20

4

Philips Semiconductors	Product specification

8-bit serial-in/serial or parallel-out shift register

74LV595

with output latches (3-State)

LOGIC DIAGRAM
	STAGE 0				STAGES 1 to 6				STAGE 7
DS	D	Q	D					Q	D	Q	Q7'
	FFO								FF7
	CP								CP
	R								R
SHCP
MR
	D	Q							D	Q
	LATCH								LATCH
	CP								CP
STCP
OE
		Q0	Q1	Q2	Q3	Q4	Q5	Q6			Q7
											SV00721

TIMING DIAGRAM

SHCP

DS

STCP

MR

OE

Z±state

Q0

Z±state

Q1

Z±state

Q6

Z±state

Q7

Q7'

SV00726

1998 Apr 20

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