Philips 74lv574 DATASHEETS
INTEGRATED CIRCUITS
74LV574
Octal D-type flip-flop;
positive edge-trigger (3-State)
Product specification
Supersedes data of 1997 Feb 03
IC24 Data Handbook
1998 Jun 10
Philips Semiconductors Product specification
74L V574Octal D-type flip-flop; positive edge-trigger (3-State)
FEA TURES
•Wide operating voltage: 1.0 to 5.5V
•Optimized for Low Voltage applications: 1.0 to 3.6V
•Accepts TTL input levels between V
•Typical V
T
amb
•Typical V
T
amb
(output ground bounce) 0.8V at VCC = 3.3V,
OLP
= 25°C
(output VOH undershoot) 2V at VCC = 3.3V,
OHV
= 25°C
= 2.7V and VCC = 3.6V
CC
•Common 3-State output enable input
•Output capability: bus driver
•I
category: MSI
CC
QUICK REFERENCE DATA
GND = 0V; T
SYMBOL
t
PHL/tPLH
f
max
C
I
C
PD
NOTES:
is used to determine the dynamic power dissipation (PD in µW)
1. C
PD
= CPD V
P
D
= input frequency in MHz; CL = output load capacity in pF;
f
i
f
= output frequency in MHz; VCC = supply voltage in V;
o
(C
2. The condition is V
= 25°C; tr =tf 2.5 ns
amb
CC
2
V
L
fo) = sum of the outputs.
CC
PARAMETER CONDITIONS TYPICAL UNIT
Propagation delay
CP to Q
n
Maximum clock frequency CL = 15pF, VCC = 3.3V 77 MHz
Input capacitance 3.5 pF
Power dissipation capacitance per flip-flop Notes 1 and 2 25 pF
2
x fi (CL V
= GND to V
I
CC
2
fo) where:
CC
DESCRIPTION
The 74LV574 is a low-voltage Si-gate CMOS device and is pin and
function compatible with 74HC/HCT574.
The 74LV574 is an octal D-type flip–flop featuring separate D-type
inputs for each flip-flop and non-inverting 3-state outputs for bus
oriented applications. A clock (CP) and an output enable (OE
are common to all flip-flops.
The eight flip-flops will store the state of their individual D-inputs that
meet the set-up and hold times requirements on the LOW-to-HIGH
CP transition.
When OE
the outputs. When OE
impedance OFF-state. Operation of the OE
state of the flip-flops.
CL = 15pF
VCC = 3.3V
is LOW, the contents of the eight flip-flops is available at
is HIGH, the outputs go to the high
input does not affect the
13 ns
) input
ORDERING AND PACKAGE INFORMA TION
PACKAGES TEMPERATURE RANGE
20-Pin Plastic DIL –40°C to +125°C 74LV574 N 74LV574 N SOT146-1
20-Pin Plastic SO –40°C to +125°C 74LV574 D 74LV574 D SOT163-1
20-Pin Plastic SSOP Type II –40°C to +125°C 74LV574 DB 74LV574 DB SOT339-1
20-Pin Plastic TSSOP Type I –40°C to +125°C 74LV574 PW 74LV574PW DH SOT360-1
PIN DESCRIPTION
PIN NUMBER SYMBOL FUNCTION
1 OE Output enabled input (active LOW)
2, 3, 4, 5,
6, 7, 8, 9
19, 18, 17, 16,
15, 14, 13, 12
10 GND Ground (0V)
11 CP
20 VCC Positive supply voltage
D0–D7 Data inputs
Q0–Q7 3-State flip-flop outputs
Clock input (LOW-to-HIGH,
edge-triggered)
OUTSIDE NORTH
AMERICA
FUNCTION TABLE
OPERATING
Load and read
Load register and
disable outputsHH↑↑lh
H = HIGH voltage level
h = HIGH voltage level one set-up time prior to the
LOW-to-HIGH CP transition
L = LOW voltage level
l = LOW voltage level one set-up time prior to the
Z = High impedance OFF-state
↑ = LOW–to–HIGH clock transition
NORTH AMERICA PKG. DWG. #
INPUTS
MODES
register
LOW-to-HIGH CP transition
OE CP Dn
LL↑↑l
FLIP-FLOPS
h
INTERNAL
L
H
L
H
OUTPUTS
Q0 to Q7
L
H
Z
Z
1998 Jun 10 853-1990 19545
2
Philips Semiconductors Product specification
74LV574Octal D-type flip-flop; positive edge-trigger (3-State)
PIN CONFIGURATION
1
OE
D0
2
3
D1
4
D2
5
D3
6
D4
7
D5
8
D6
9
D7
10
GND
LOGIC SYMBOL
2
D0
3
D1
4
D2
5
D3
6
D4
7
D5
8
D6
9
D7
CP
OE
LOGIC SYMBOL (IEEE/IEC)
20
19
18
17
16
15
14
13
12
11
SV00714
VCC
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
CP
11
1
2
3
4
5
6
7
8
9
EN
1D
C1
19
18
17
16
15
14
13
12
SV00716
FUNCTIONAL DIAGRAM
2
11
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
1
19
18
17
16
15
14
13
12
SV00715
D0
3
D1
4
D2
5
D3
6
D4
7
D5
8
D6
9
D7
11
CP
1
OE
FF1 to FF8
3–STATE
OUTPUTS
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
SV00717
19
18
17
16
15
14
13
12
1998 Jun 10
3
Philips Semiconductors Product specification
74LV574Octal D-type flip-flop; positive edge-trigger (3-State)
LOGIC DIAGRAM
D0
D
D1 D2 D3 D4 D5 D6 D7
Q
D Q
D Q
D Q
D Q
D Q
D Q
D Q
CP
FF1 FF2 FF3 FF4 FF5 FF6 FF7 FF8
CP
OE
ABSOLUTE MAXIMUM RA TINGS
Q0
CP
CP
Q1 Q2 Q3 Q4 Q5 Q6 Q7
CP
CP
CP
CP
1, 2
CP
SV00342
In accordance with the Absolute Maximum Rating System (IEC 134)
Voltages are referenced to GND (ground = 0V)
SYMBOL
V
CC
±I
IK
±I
OK
±I
O
±I
GND
±I
CC
T
stg
P
TOT
DC supply voltage –0.5 to +7.0 V
DC input diode current VI < –0.5 or VI > VCC + 0.5V 20 mA
DC output diode current VO < –0.5 or VO > VCC + 0.5V 50 mA
DC output source or sink current
– bus driver outputs
DC VCC or GND current for types with
,
–bus driver outputs
Storage temperature range –65 to +150 °C
Power dissipation per package
–plastic DIL
–plastic mini-pack (SO)
–plastic shrink mini-pack (SSOP and TSSOP)
PARAMETER CONDITIONS RATING UNIT
–0.5V < VO < VCC + 0.5V 35 mA
70 mA
for temperature range: –40 to +125°C
above +70°C derate linearly with 12mW/K
above +70°C derate linearly with 8 mW/K
above +60°C derate linearly with 5.5 mW/K
750
500
400
mW
NOTES:
1. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the
device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to
absolute-maximum-rated conditions for extended periods may affect device reliability .
2. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
RECOMMENDED OPERATING CONDITIONS
SYMBOL PARAMETER CONDITIONS MIN TYP. MAX UNIT
1
1.0 3.3 5.5 V
CC
CC
–40
–40
–
–
–
–
–
–
–
–
+85
+125
500
200
100
50
T
V
V
tr, t
CC
V
amb
DC supply voltage See Note
Input voltage 0 – V
I
Output voltage 0 – V
O
Operating ambient temperature range in free
air
Input rise and fall times
f
NOTES:
1. The LV is guaranteed to function down to V
1998 Jun 10
See DC and AC
characteristics
VCC = 1.0V to 2.0V
VCC = 2.0V to 2.7V
V
= 2.7V to 3.6V
CC
VCC = 3.6V to 5.5V
= 1.0V (input levels GND or VCC); DC characteristics are guaranteed from VCC = 1.2V to VCC = 5.5V.
CC
4
V
V
°C
ns/V
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