Philips 74LV573PW, 74LV573N, 74LV573D Datasheet
INTEGRATED CIRCUITS
74LV573
Octal D-type transparent latch (3-State)
Product specification
Supersedes data of 1997 Jun 06
IC24 Data Handbook
1998 Jun 10
Philips Semiconductors Product specification
74L V573Octal D-type transparent latch (3-State)
FEA TURES
•Wide operating voltage: 1.0 to 5.5V
•Optimized for Low Voltage applications: 1.0V to 3.6V
•Accepts TTL input levels between V
•Typical V
T
amb
•Typical V
T
amb
(output ground bounce) < 0.8V at V
OLP
= 25°C
(output VOH undershoot) > 2V at V
OHV
= 25°C
= 2.7V and V
CC
CC
CC
= 3.6V
CC
= 3.3V ,
= 3.3V ,
•Inputs and outputs on opposite sides of package allowing easy
interface with microprocessors
•Useful as input or output port for microprocessors/microcomputer
•Common 3-State output enable input
•Output capability: bus driver
•I
category: MSI
CC
QUICK REFERENCE DATA
GND = 0V; T
SYMBOL
t
PHL/tPLH
C
I
C
PD
NOTES:
1. C
is used to determine the dynamic power dissipation (PD in µW)
PD
= CPD V
P
D
f
= input frequency in MHz; CL = output load capacity in pF;
i
= output frequency in MHz; VCC = supply voltage in V;
f
o
(C
2. The condition is V
= 25°C; tr = tf 2.5 ns
amb
CC
2
V
L
fo) = sum of the outputs.
CC
PARAMETER CONDITIONS TYPICAL UNIT
Propagation delay
Dn to Qn
LE to Qn
Input capacitance 3.5 pF
Power dissipation capacitance per latch Notes 1, 2 26 pF
2
x fi (CL V
= GND to V
I
CC.
2
fo) where:
CC
DESCRIPTION
The 74LV573 is a low-voltage Si-gate CMOS device that is pin and
function compatible with 74HC/HCT573.
The 74LV573 is an octal D-type transparent latch featuring separate
D-type inputs for each latch and 3-State outputs for bus oriented
applications. A latch enable (LE) input and an output enable (OE
input are common to all internal latches.
The ‘573’ consists of eight D-type transparent latches with 3-State
true outputs. When LE is HIGH, data at the D
latches. In this condition the latches are transparent, i.e., a latch
output will change each time its corresponding D-input changes.
When LE is LOW the latches store the information that was present
at the D-inputs a set-up time preceding the HIGH-to-LOW transition
of LE. When OE
available at the outputs. When OE
high impedance OFF-state. Operation of the OE
affect the state of the latches.
The ‘573’ is functionally identical to the ‘563’ and the ‘373’, but the
‘563’ has inverted outputs and the ‘373’ has a different pin
arrangement.
CL = 15pF
VCC = 3.3V 12
is LOW, the contents of the eight latches are
is HIGH, the outputs go to the
13
inputs enters the
n
input does not
)
ns
ORDERING AND PACKAGE INFORMA TION
PACKAGES TEMPERATURE RANGE
20-Pin Plastic DIL –40°C to +125°C 74LV573 N 74LV573 N SOT146-1
20-Pin Plastic SO –40°C to +125°C 74LV573 D 74LV573 D SOT163-1
20-Pin Plastic SSOP Type II –40°C to +125°C 74LV573 DB 74LV573 DB SOT339-1
20-Pin Plastic TSSOP Type I –40°C to +125°C 74LV573 PW 74LV573PW DH SOT360-1
OUTSIDE NORTH
AMERICA
NORTH AMERICA PKG. DWG. #
PIN DESCRIPTION
PIN NUMBER SYMBOL FUNCTION
1 OE Output enabled input (active LOW)
2, 3, 4, 5,
6, 7, 8, 9
19, 18, 17, 16,
15, 14, 13, 12
10 GND Ground (0V)
11 LE Latch enable input (active HIGH)
20 VCC Positive supply voltage
1998 Jun 10 853-1989 19545
D0–D7 Data inputs
Q0–Q7 Data outputs
2
Philips Semiconductors Product specification
OPERATING MODES
74LV573Octal D-type transparent latch (3-State)
FUNCTION TABLE
INPUTS
OE LE Dn
Enable and read register
(transparent mode)
Latch and read register
Latch register and disable outputs
L
L
L
L
H
H
H
H
L
L
L
L
L
H
I
h
I
h
H = HIGH voltage level
h = HIGH voltage level one set-up time prior to the HIGH-to-LOW LE transition
L = LOW voltage level
I = LOW voltage level one set-up time prior to the HIGH-to-LOW LE transition
Z = High impedance OFF-state
INTERNAL
LATCHES
L
H
L
H
L
H
OUTPUTS
Q0 to Q7
L
H
L
H
Z
Z
PIN CONFIGURATION
OE
1
D0
2
D1
3
D2
4
D3
5
D4
6
D5
7
D6
8
D7
9
10
GND
20
19
18
17
16
15
14
13
12
11
SV00701
VCC
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
LE
LOGIC SYMBOL
2
3
4
5
6
7
8
9
1
OE
D0
D1
D2
D3
D4
D5
D6
D7
LE
11
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
19
18
17
16
15
14
13
12
SV00702
1998 Jun 10
3
Philips Semiconductors Product specification
74LV573Octal D-type transparent latch (3-State)
LOGIC SYMBOL (IEEE/IEC)
11
1
2
3
4
5
6
7
8
9
C1
EN1
1D
LOGIC DIAGRAM
D
0
D
FUNCTIONAL DIAGRAM
2
D0
3
D1
4
19
18
17
16
15
14
13
12
D2
5
D3
6
D4
7
D5
8
D6
9
D7
11
LE
1
OE
LATCH
1 TO 8
3-STATE
OUTPUTS
SV00703
1
D
2
D
3
D
4
D
5
D
6
D
7
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
SV00704
19
18
17
16
15
14
13
12
OE
Q
D
LATCH
1
LE
LE
LE
Q0
D
LATCH
2
LE
Q
LE
Q1
D
LATCH
3
LE
Q
LE
Q2
D
LATCH
4
LE
Q
LE
Q3
D
LATCH
5
LE
Q
LE
Q4
D
LATCH
6
LE
Q
LE
Q5
D
LATCH
7
LE
Q
LE
Q6
D
LATCH
8
LE
Q
LE
Q7
SV00661
1998 Jun 10
4
Philips Semiconductors Product specification
P
mW
74LV573Octal D-type transparent latch (3-State)
ABSOLUTE MAXIMUM RATINGS
1, 2
In accordance with the Absolute Maximum Rating System (IEC 134)
Voltages are referenced to GND (ground = 0V)
SYMBOL
V
CC
±I
IK
±I
OK
±I
O
±I
GND
±I
CC
T
stg
DC supply voltage –0.5 to +7.0 V
DC input diode current VI < –0.5 or VI > VCC + 0.5V 20 mA
DC output diode current VO < –0.5 or VO > VCC + 0.5V 50 mA
DC output source or sink current
– bus driver outputs
DC VCC or GND current for types with
,
–bus driver outputs
Storage temperature range –65 to +150 °C
PARAMETER CONDITIONS RATING UNIT
–0.5V < VO < VCC + 0.5V 35 mA
70 mA
Power dissipation per package for temperature range: –40 to +125°C
–plastic DIL above +70°C derate linearly with 12mW/K 750
tot
–plastic mini-pack (SO) above +70°C derate linearly with 8 mW/K 500
–plastic shrink mini-pack (SSOP and TSSOP) above +60°C derate linearly with 5.5 mW/K 400
NOTES:
1. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the
device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to
absolute-maximum-rated conditions for extended periods may affect device reliability .
2. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
RECOMMENDED OPERATING CONDITIONS
SYMBOL PARAMETER CONDITIONS MIN TYP. MAX UNIT
V
CC
V
V
T
amb
tr, t
NOTE:
1. The LV is guaranteed to function down to V
DC supply voltage See Note 1 1.0 3.3 5.5 V
Input voltage 0 – V
I
Output voltage 0 – V
O
Operating ambient temperature range in free
air
Input rise and fall times
f
= 1.0V (input levels GND or VCC); DC characteristics are guaranteed from VCC = 1.2V to VCC = 5.5V.
CC
See DC and AC
characteristics
VCC = 1.0V to 2.0V
VCC = 2.0V to 2.7V
VCC = 2.7V to 3.6V
VCC = 3.6V to 5.5V
–40
–40
–
–
–
–
–
–
–
–
CC
CC
+85
+125
500
200
100
50
V
V
°C
ns/V
1998 Jun 10
5
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