Philips 74lv4094 DATASHEETS
INTEGRATED CIRCUITS
74LV4094
8-stage shift-and-store bus register
Product specification 1998 Jun 23
Philips Semiconductors Product specification
74L V40948-stage shift-and-store bus register
FEA TURES
•Optimized for low voltage applications: 1.0 to 3.6 V
•Accepts TTL input levels between V
•Typical V
T
amb
•Typical V
T
amb
(output ground bounce) < 0.8 V at V
OLP
= 25°C
(output VOH undershoot) > 2 V at V
OHV
= 25°C
= 2.7 V and V
CC
•Output capability: standard
•I
category: MSI
CC
Applications:
•Serial-to-parallel data conversion
•Remote control holding register
QUICK REFERENCE DATA
GND = 0 V; T
= 25°C; tr =t
amb
SYMBOL
Propagation delay
CP to QS
t
PHL/tPLH
CP to QS
CP to QP
STR to QP
f
MAX
C
C
I
PD
Maximum clock frequency
Input capacitance 3.5 pF
Power dissipation capacitance per gate
NOTE:
1. C
is used to determine the dynamic power dissipation (PD in µW)
PD
= CPD × V
P
D
f
= input frequency in MHz; CL = output load capacity in pF;
i
= output frequency in MHz; VCC = supply voltage in V;
f
o
(C
× V
L
2
CC
2
× fo) = sum of the outputs.
CC
≤ 2.5 ns
f
PARAMETER CONDITIONS TYPICAL UNIT
1
2
n
n
× fi (CL × V
2
× fo) where:
CC
CC
CC
= 3.6 V
CC
= 3.3 V,
= 3.3 V,
CL = 15 pF;
VCC = 3.3 V
VCC = 3.3 V
VI = GND to V
DESCRIPTION
The 74LV4094 is a low-voltage Si-gate CMOS device and is pin and
function compatible with 74HC/HCT4094.
The 74LV4094 is an 8-stage serial shift register having a storage
latch associated with each stage for strobing data from the serial
input (D) to the parallel buffered 3-State outputs (QP
parallel outputs may be connected directly to the common bus lines.
Data is shifted on the positive-going clock (CP) transitions. The data
in each shift register is transferred to the storage register when the
strobe input (STR) is HIGH. Data in the storage register appears at
the outputs whenever the output enable input (OE) signal is HIGH.
Two serial outputs (QS
and QS2) are available for cascading a
1
number of 74L V4094 devices. Data is available at QS
positive-going clock edges to allow high-speed operation in
cascaded systems in which the clock rise time is fast. The same
serial information is available at QS
on the next negative going
2
clock edge and is for cascading 74LV4094 devices when the clock
rise time is slow.
14
13
18
17
95
CC
NO TAG
83 pF
to OP7). The
0
on the
1
ns
MHz
ORDERING INFORMATION
PACKAGES TEMPERATURE RANGE OUTSIDE NORTH AMERICA NORTH AMERICA PKG. DWG. #
16-Pin Plastic DIL –40°C to +125°C 74LV4094 N 74LV4094 N SOT38-4
16-Pin Plastic SO –40°C to +125°C 74LV4094 D 74LV4094 D SOT109-1
PIN CONFIGURATION
1
STR
2
D
3
CP
4
QP
0
5
QP
1
6
QP
2
7
QP
3
8
GND
1998 Jun 23 853-2078 19619
16
15
14
13
12
11
10
9
SV01611
V
OE
QP
QP
QP
QP
QS
QS
CC
4
5
6
7
2
1
PIN DESCRIPTION
PIN NUMBER SYMBOL FUNCTION
1 STR Strobe input
2 D Serial input
3 CP Clock input
4, 5, 6, 7, 14,
13, 12, 11
8 GND Ground (0 V)
9, 10 QS1, QS
15 OE Output enable input
16 V
2
QP0 to QP7Parallel outputs
Serial outputs
2
CC
Positive supply voltage
Philips Semiconductors Product specification
74LV40948-stage shift-and-store bus register
LOGIC SYMBOL
3
CP
2
D
FUNCTIONAL DIAGRAM
D
2
CP
3
STR
1
8-STATE SHIFT
REGISTER
8-BIT STORAGE
REGISTER
OE
LOGIC SYMBOL (IEEE/IEC)
1
STR
QS
QS
QP
QP
QP
QP
QP
QP
QP
QP
15
9
1
10
2
4
0
5
1
6
2
7
3
14
4
13
5
12
6
11
7
SV01612
QS
2
10
QS
1
9
1
C2
15
EN3
3
2
SRG8
C1/
1D
2D
3
4
5
6
7
14
13
12
11
9
10
SV01613
OE
15
QP0QP1QP2QP3QP4Q51QP6QP
4 5 6 7 14 13 12 11
LOGIC DIAGRAM
3-STATE OUTPUTS
D
CP
STR
OE
7
SV01614
STAGE 0 STAGE 7
D
Q
FF0 FF7
CP
D
Q
latch latch
CP
QP0QP
STAGES 1 TO 6
D
CP
QP
1
QP
2
D
CP
D
CP
Q
Q
Q
QP
3
5
QP
QP
4
6
QP
’
Q
7
DCPQ
latch
7
QS
2
SV01615
1998 Jun 23
3
Philips Semiconductors Product specification
74LV40948-stage shift-and-store bus register
FUNCTION TABLE
INPUTS PARALLEL OUTPUT SERIAL OUTPUTS
CP OE STR D QP
0
↑ L X X Z Z Q’
↓ L X X Z Z NC QP
↑ H L X NC NC Q’
↑ H H L L QP
↑ H H H H QP
↓ H H H NC NC NC QP
NOTES:
H = HIGH voltage level
L = LOW voltage level
X = don’t care
↑ = LOW-to–HIGH CP transition
↓ = HIGH-to-LOW CP transition
= the information in the 8th register stage is transferred to the
Q’
6
th
8
register stage and QSn clock edge.
Z = high impedance OFF-state
NC = no change
TIMING DIAGRAM
CPCLOCK INPUT
QP
n–1
n–1
n
QS
Q’
Q’
1
6
6
6
6
QS
NC
NC
NC
NC
2
7
7
DATA INPUT
STROBE INPUT
OUTPUT ENABLE INPUT
INTERNAL Q’0 (FF0)
OUTPUT
INTERNAL Q’6 (FF6)
OUTPUT
SERIAL OUTPUT
SERIAL OUTPUT
STR
OE
QP
QP
QS
QS
D
0
6
1
2
Z–state
Z–state
SV01616
1998 Jun 23
4
Philips Semiconductors Product specification
74LV40948-stage shift-and-store bus register
ABSOLUTE MAXIMUM RATINGS
NO TAG, NO TAG
In accordance with the Absolute Maximum Rating System (IEC 134).
Voltages are referenced to GND (ground = 0 V).
SYMBOL
V
CC
I
IK
I
OK
I
O
I
GND
I
CC
T
stg
P
TOT
DC supply voltage –0.5 to +7.0 V
DC input diode current VI < –0.5 or VI > VCC + 0.5V 20 mA
DC output diode current VO < –0.5 or VO > VCC + 0.5V 50 mA
DC output source or sink current
– standard outputs
DC VCC or GND current for types with
,
– standard outputs 50
Storage temperature range –65 to +150 °C
Power dissipation per package
– plastic DIL
– plastic mini-pack (SO)
– plastic shrink mini-pack (SSOP and TSSOP)
PARAMETER CONDITIONS RATING UNIT
–0.5V < VO < VCC + 0.5V
25
mA
mA
for temperature range: –40 to +125°C
above +70°C derate linearly with 12 mW/K
above +70°C derate linearly with 8 mW/K
above +60°C derate linearly with 5.5 mW/K
750
500
400
mW
NOTES:
1. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the
device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to
absolute-maximum-rated conditions for extended periods may affect device reliability .
2. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
RECOMMENDED OPERATING CONDITIONS
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNIT
V
V
V
T
amb
tr, t
NOTE:
1. The LV is guaranteed to function down to V
DC supply voltage See Note NO TAG 1.0 3.3 3.6 V
CC
Input voltage 0 – V
I
Output voltage 0 – V
O
Operating ambient temperature range in free air
Input rise and fall times except for
f
Schmitt-trigger inputs
CC
See DC and AC
characteristics
VCC = 1.0V to 2.0V
VCC = 2.0V to 2.7V
VCC = 2.7V to 3.6V
= 1.0V (input levels GND or VCC); DC characteristics are guaranteed from VCC = 1.2V to VCC = 5.5V.
–40
–40
–
–
–
–
–
–
CC
CC
+85
+125
500
200
100
V
V
°C
ns/V
1998 Jun 23
5
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