INTEGRATED CIRCUITS
74LV4066
Quad bilateral switches
Product specification |
1998 Jun 23 |
Supersedes data of 1996 Jan 01
IC24 Data Handbook
m n r
Philips Semiconductors |
Product specification |
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Quad bilateral switches |
74LV4066 |
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FEATURES
•Optimized for Low Voltage applications: 1.0V to 6.0V
•Accepts TTL input levels between VCC = 2.7 V and VCC = 3.6 V
•Typical VOLP (output ground bounce) < 0.8 V at VCC = 3.3 V, Tamb = 25 °C.
• Very low typ ªONº resistance:
25 at VCC ± VEE = 4.5 V
35 at VCC ± VEE = 3.0 V
60 at VCC ± VEE = 2.0 V
•Output capability: non-standard
•ICC category: SSI
DESCRIPTION
The 74LV4066 is a low-voltage Si-gate CMOS device that is pin and function compatible with 74HC/HCT4066.
The 74LV4066 has four independent analog switches. Each switch has two input/output terminals (nY, nZ) and an active HIGH enable input (nE). When nE is LOW the corresponding analog switch is turned off.
The 74LV4066 has an on resistance which is dramatically reduced in comparison with 74HCT4066.
FUNCTION TABLE
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INPUTS |
SWITCH |
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nE |
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L |
off |
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H |
on |
NOTES: |
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H |
= |
HIGH voltage level |
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L |
= |
LOW voltage level |
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QUICK REFERENCE DATA
GND = 0 V; Tamb = 25°C; tr =tf 2.5 ns
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SYMBOL |
PARAMETER |
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CONDITIONS |
TYPICAL |
UNIT |
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t |
/t |
Turn ªONº time: nE to V |
C |
L |
= 15pF |
10 |
ns |
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PZH PZL |
OS |
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RL = 1K |
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t |
/t |
Turn ªOFFº time: nE to V |
13 |
ns |
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VCC= 3.3V |
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PHZ PLZ |
OS |
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CI |
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Input capacitance |
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3.5 |
pF |
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CPD |
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Power dissipation capacitance per switch |
Notes 1, 2 |
11 |
pF |
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CS |
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Maximum switch capacitances |
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8 |
pF |
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NOTES:
1. CPD is used to determine the dynamic power dissipation (PD in mW) PD = CPD × VCC2 × fi (CL × VCC2 × fo) where:
fi = input frequency in MHz; CL = output load capacity in pF;
fo = output frequency in MHz; Cs = maximum switch capacitance in pF;{(CL + CS) × VCC2 × Fo} = sum of the outputs.
VCC = supply voltage in V.
2. The condition is VI = GND to VCC.
ORDERING AND PACKAGE INFORMATION
TYPE NUMBER |
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PACKAGES |
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PINS |
PACKAGE |
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MATERIAL |
CODE |
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74LV4066N |
16 |
DIL |
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Plastic |
SOT27-1 |
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74LV4066D |
16 |
SO |
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Plastic |
SOT108-1 |
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74LV4066DB |
16 |
SSOP |
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Plastic |
SOT337-1 |
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74LV4066PW |
16 |
TSSOP |
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Plastic |
SOT402-1 |
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PIN CONFIGURATION
1Y |
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PIN DESCRIPTION |
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1 |
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VCC |
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1Z |
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14 |
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PIN |
SYMBOL |
FUNCTION |
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2 |
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13 |
1E |
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NUMBER |
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4E |
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2Z |
3 |
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12 |
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1, 4, 8, 11 |
1Y ± 4Y |
Independent inputs/outputs |
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4Y |
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2Y |
4 |
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11 |
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2, 3, 9, 10 |
1Z ± 4Z |
Independent inputs/outputs |
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2E |
5 |
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10 |
4Z |
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13, 5, 6, 12 |
1E to 4E |
Enable input (active HIGH) |
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3Z |
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3E |
6 |
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9 |
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7 |
GND |
Ground (0V) |
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3Y |
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GND |
7 |
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8 |
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14 |
VCC |
Positive supply voltage |
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SV01669 |
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1998 Jun 23 |
2 |
853-2077 19619 |
Philips Semiconductors |
Product specification |
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Quad bilateral switches |
74LV4066 |
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FUNCTIONAL DIAGRAM |
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IEC LOGIC SYMBOL |
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1 |
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1Y |
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1Z |
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2 |
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1 |
1 |
1 |
2 |
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1E |
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1 |
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2 |
13# |
X1 |
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13 |
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2Y |
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2Z |
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13# |
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4 |
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3 |
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4 |
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3 |
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4 |
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3 |
1 |
1 |
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2E |
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5# |
X1 |
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5 |
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5# |
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8 |
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9 |
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3Y |
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3Z |
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8 |
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9 |
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8 |
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9 |
1 |
1 |
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3E |
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6# |
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6 |
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6# |
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X1 |
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4Y |
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4Z |
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11 |
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10 |
11 |
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10 |
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11 |
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10 |
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1 |
1 |
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4E |
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12# |
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12# |
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12 |
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X1 |
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(a) |
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(b) |
SV01671 |
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SV01670 |
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SCHEMATIC DIAGRAM (ONE SWITCH)
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nY |
nE |
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VCC |
VCC |
GND |
nZ |
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SV01672 |
RECOMMENDED OPERATING CONDITIONS
SYMBOL |
PARAMETER |
CONDITIONS |
MIN |
TYP |
MAX |
UNIT |
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VCC |
DC supply voltage |
See Note 1 |
1.0 |
3.3 |
6 |
V |
VI |
Input voltage |
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0 |
± |
VCC |
V |
VO |
Output voltage |
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0 |
± |
VCC |
V |
Tamb |
Operating ambient temperature range in free air |
See DC and AC |
±40 |
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+85 |
°C |
characteristics |
±40 |
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+125 |
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VCC = 1.0V to 2.0V |
± |
± |
500 |
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tr, tf |
Input rise and fall times |
VCC = 2.0V to 2.7V |
± |
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200 |
ns/V |
VCC = 2.7V to 3.6V |
± |
± |
100 |
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VCC = 3.6V to 5.5V |
± |
± |
50 |
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NOTE:
1. The LV is guaranteed to function down to VCC = 1.0V (input levels GND or VCC); DC characteristics are guaranteed from VCC = 1.2V to VCC = 5.5V.
ABSOLUTE MAXIMUM RATINGS1, 2
In accordance with the Absolute Maximum Rating System (IEC 134).
Voltages are referenced to GND (ground = 0 V).
SYMBOL |
PARAMETER |
CONDITIONS |
RATING |
UNIT |
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VCC |
DC supply voltage |
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±0.5 to +7.0 |
V |
"IIK |
DC input diode current |
VI < ±0.5 or VI > VCC + 0.5V |
20 |
mA |
"IOK |
DC output diode current |
VO < ±0.5 or VO > VCC + 0.5V |
50 |
mA |
"IO |
DC switch current |
±0.5V < VO < VCC + 0.5V |
25 |
mA |
Tstg |
Storage temperature range |
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±65 to +150 |
°C |
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Power dissipation per package |
for temperature range: ±40 to +125°C |
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PTOT |
± plastic DIL |
above +70°C derate linearly with 12 mW/K |
750 |
mW |
± plastic mini-pack (SO) |
above +70°C derate linearly with 8 mW/K |
500 |
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± plastic shrink mini-pack (SSOP and TSSOP) |
above +60°C derate linearly with 5.5 mW/K |
400 |
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NOTES:
1.Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under ªrecommended operating conditionsº is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
2.The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
1998 Jun 23 |
3 |
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