Philips 74LV4060PW, 74LV4060N, 74LV4060DB, 74LV4060D Datasheet

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INTEGRATED CIRCUITS

74LV4060

14-stage binary ripple counter with oscillator

Product specification

1998 Jun 23

m n r

Philips Semiconductors

Product specification

 

 

 

 

 

14-stage binary ripple counter with oscillator

74LV4060

 

 

 

 

 

 

FEATURES

Wide operating voltage: 1.0 to 5.5 V

Optimized for Low Voltage applications: 1.0 to 3.6 V

Accepts TTL input levels between VCC = 2.7 V and VCC = 3.6 V

Typical VOLP (output ground bounce) < 0.8 V at VCC = 3.3 V, Tamb = 25 C.

Typical VOHV (output VOH undershoot) > 2 V at VCC = 3.3 V, Tamb

= 25 C.

All active components on chip

RC or crystal oscillator configuration

Output capability: standard (except for RTC and CTC)

ICC category: MSI

QUICK REFERENCE DATA

GND = 0 V; Tamb = 25 C; tr = tf < 2.5 ns

APPLICATIONS

Control Counters

Timers

Frequency Dividers

Time-delay circuits

DESCRIPTION

The 74LV4060 is a low-voltage Si-gate CMOS device and is pin and function compatible with the 74HC/HCT4060.

The 74LV4060 is a 14-stage ripple-carry counter/divider and oscillator with three oscillator terminals (RS, RTC and CTC), ten buffered outputs (Q3 to Q9 and Q11 to Q13) and an overriding asynchronous master reset (MR). The oscillator configuration allows design of either RC or crystal oscillator circuits. The oscillator may be replaced by an external clock signal at input RS. In this case, keep the oscillator pins (RTC and CTC) floating.

The counter advances on the negative-going transition of RS. A HIGH level on MR resets the counter (Q3 to Q9 and Q11 to

Q13 = LOW), independent of the other input conditions.

SYMBOL

PARAMETER

CONDITIONS

TYPICAL

UNIT

 

 

 

 

 

 

Propagation delay

CL = 15 pF

 

 

 

RS to Q3

VCC = 3.3 V

29

 

tPHL/tPLH

Qn to Qn+1

 

6

ns

tPHL

MR to Qn

 

16

 

fmax

Maximum clock frequency

 

99

MHz

C1

Input capacitance

 

3.5

pF

CPD

Power dissipation capacitance per package

Notes 1, 2 and 3

40

pF

 

 

 

 

 

 

NOTES:

1.CPD is used to determine the dynamic power

dissipation (PD in W)

PD = CPD x VCC2 x fi + (CL x VCC2 x fo) where:

fi = input frequency in MHz; CL = output load capacity in pF;

fo = output frequency in MHz; VCC = supply voltage in V;(CL x VCC2 x fo) = sum of the outputs.

2.The condition is V1 = GND to VCC

3.For formula on dynamic power dissipation, see the following pages.

ORDERING INFORMATION

PACKAGES

TEMPERATURE RANGE

OUTSIDE NORTH AMERICA

NORTH AMERICA

PKG. DWG. #

 

 

 

 

 

16-Pin Plastic DIL

±40°C to +125°C

74LV4060 N

74LV4060 N

SOT38-4

 

 

 

 

 

16-Pin Plastic SO

±40°C to +125°C

74LV4060 D

74LV4060 D

SOT109-1

 

 

 

 

 

16-Pin Plastic SSOP Type II

±40°C to +125°C

74LV4060 DB

74LV4060 DB

SOT338-1

 

 

 

 

 

16-Pin Plastic TSSOP Type I

±40°C to +125°C

74LV4060 PW

74LV4060PW DH

SOT403-1

 

 

 

 

 

1998 Jun 23

2

853-2076 19619

Philips Semiconductors

Product specification

 

 

 

14-stage binary ripple counter with oscillator

74LV4060

 

 

 

PIN DESCRIPTION

 

 

 

 

 

 

LOGIC SYMBOL

 

 

 

 

PIN NO.

SYMBOL

 

 

FUNCTION

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

1, 2, 3

Q11 to Q13

Counter outputs

 

 

10

9

 

 

7, 5, 4, 6,

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Q3 to Q9

Counter outputs

 

 

 

 

 

 

 

 

RTC CTC

 

 

15, 13, 15

 

 

11

RS

 

 

 

 

Q3

 

7

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

8

GND

 

 

Ground (0 V)

 

 

 

 

 

 

Q4

 

5

 

 

 

 

 

 

 

 

 

 

 

 

 

 

12

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

MR

 

 

 

 

Q5

 

4

9

CTC

 

 

External capacitor connection

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Q6

 

6

10

RTC

 

 

External resistor connection

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Q7

 

14

 

 

 

 

 

 

 

 

 

 

 

 

11

RS

 

 

Clock input/oscillator pin

 

 

 

 

 

 

 

 

 

Q8

 

13

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Q9

 

15

12

MR

 

 

Master reset

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Q11

 

1

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

16

VCC

 

 

Positive supply voltage

 

 

 

 

 

 

 

 

 

Q12

 

2

 

 

 

 

 

 

 

 

 

 

 

 

PIN CONFIGURATION

 

 

 

 

 

 

 

 

 

 

Q13

 

3

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

SV00307

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Q11

1

 

 

 

 

16

VCC

 

 

 

 

 

Q12

 

 

 

 

 

 

Q9

 

 

 

 

 

2

 

 

 

15

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Q13

3

 

 

 

14

Q7

 

 

 

 

 

 

 

 

 

 

 

 

Q8

 

 

 

 

 

Q5

4

 

 

 

13

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Q4

5

 

 

 

12

MR

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Q6

6

 

 

 

11

RS

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Q3

7

 

 

 

10

RTC

 

 

 

 

 

GND

 

 

 

 

 

 

CTC

 

 

 

 

 

8

 

 

 

9

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

SV00308

LOGIC SYMBOL (IEEE/IEC)

 

 

CTR14

 

 

3

9

CX

!G

10

RX

+

 

 

11

RCX

 

12

 

CT

 

 

 

CT = 0

 

 

9

 

 

11

 

 

13

 

 

(a)

 

 

CTR14

 

 

7

 

3

 

7

 

 

5

 

 

 

 

5

 

 

 

 

4

 

 

 

 

4

 

 

 

 

 

 

 

 

 

 

6

11

&

+

 

6

 

14

12

 

 

14

 

CT

 

 

 

13

 

 

 

13

 

 

 

 

CT = 0

 

 

 

15

 

9

 

15

 

 

1

 

11

 

1

 

 

2

 

 

 

 

2

 

 

 

 

3

 

13

 

3

 

 

 

 

 

 

 

 

(b)

SV00311

1998 Jun 23

3

Philips Semiconductors

Product specification

 

 

 

14-stage binary ripple counter with oscillator

74LV4060

 

 

 

DYNAMIC POWER DISSIPATION

GND = 0 V; Tamb = 25 C

PARAMETER

 

VCC

 

 

 

 

 

 

 

 

TYPICAL FORMULA FOR P

( W)1

 

 

 

 

 

 

 

(V)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

D

 

 

 

 

 

 

 

 

 

1.2

 

C

PD

x f

osc

x V

2 + (C

L

x V

CC

2 x f

) + 2C

x V

CC

2 x f

osc

+ 16 x V

 

Total dynamic power dissipation when

 

 

 

 

 

CC

 

 

o

 

t

 

CC

2.0

 

C

PD

x f

osc

x V

2 + (C

L

x V

CC

2 x f

) + 2C

x V

CC

2 x f

osc

+ 460 x V

 

using the on±chip oscillator (PD)

 

 

 

 

 

CC

 

 

o

 

t

 

CC

3.0

 

C

PD

x f

osc

x V

2 + (C

L

x V

CC

2 x f

) + 2C

x V

CC

2 x f

osc

+ 1000 x V

CC

 

 

 

 

 

 

 

 

 

 

 

CC

 

 

o

 

t

 

 

NOTE:

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

1. Where: fo = output frequency in MHz; fosc

= oscillator frequency in MHz;

 

 

 

 

 

 

 

 

 

(C

L

x V

CC

2

x f ) = sum of the outputs; C

L

= output load capacitance in pF;

 

 

 

 

 

 

 

 

 

o

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Ct = timing capacitance in pF; VCC = supply voltage in V.

FUNCTIONAL DIAGRAM

 

10

9

 

 

 

 

 

 

 

 

 

 

RTC

CTC

 

 

 

 

 

 

 

 

 

11

RS

CP

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

14-stage binary counter

 

 

 

 

 

 

CD

 

 

 

 

 

 

 

 

 

12

MR

Q3

Q4

Q5

Q6

Q7

Q8

Q9

Q11

Q12

Q13

 

 

7

5

4

6

14

13

15

1

2

3

 

 

 

 

 

 

 

 

 

 

 

SV00312

LOGIC DIAGRAM

CTC

 

 

 

 

 

RTC

FF4

FF10

FF12

 

FF14

FF1

 

RS

 

 

 

 

 

CP

 

 

 

 

 

 

Q

 

 

 

 

CD

 

 

 

 

 

MR

 

Q3

Q9

Q11

Q13

 

 

 

 

 

 

 

SV00313

1998 Jun 23

4

Philips 74LV4060PW, 74LV4060N, 74LV4060DB, 74LV4060D Datasheet

Philips Semiconductors

Product specification

 

 

 

14-stage binary ripple counter with oscillator

74LV4060

 

 

 

TIMING DIAGRAM

1

2

4

8

16

32

64

128

256

512

1.024

2.048

4.096

8.192

16.384

RS

MR

Q3

Q4

Q5

Q6

Q7

Q8

Q9

Q11

Q12

Q13

SV00309

ABSOLUTE MAXIMUM RATINGS1, 2

In accordance with the Absolute Maximum Rating System (IEC 134)

Voltages are referenced to GND (ground = 0V)

SYMBOL

PARAMETER

CONDITIONS

RATING

UNIT

 

 

 

 

 

VCC

DC supply voltage

 

±0.5 to +7.0

V

±IIK

DC input diode current

VI < ±0.5 or VI > VCC + 0.5V

20

mA

±IOK

DC output diode current

VO < ±0.5 or VO > VCC + 0.5V

50

mA

±IO

DC output source or sink current

±0.5V < VO < VCC + 0.5V

 

mA

± standard outputs

25

 

 

 

 

 

±IGND,

DC VCC or GND current for types with

 

 

mA

±standard outputs

 

50

±ICC

 

 

 

 

Tstg

Storage temperature range

 

±65 to +150

°C

 

Power dissipation per package

for temperature range: ±40 to +125°C

 

 

PTOT

±plastic DIL

above +70°C derate linearly with 12mW/K

750

mW

±plastic mini-pack (SO)

above +70°C derate linearly with 8 mW/K

500

 

±plastic shrink mini-pack (SSOP and TSSOP)

above +60°C derate linearly with 5.5 mW/K

400

 

 

 

 

 

 

NOTES:

1.Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under ªrecommended operating conditionsº is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

2.The input and output voltage ratings may be exceeded if the input and output current ratings are observed.

1998 Jun 23

5

Philips Semiconductors

Product specification

 

 

 

14-stage binary ripple counter with oscillator

74LV4060

 

 

 

RECOMMENDED OPERATING CONDITIONS

SYMBOL

PARAMETER

CONDITIONS

MIN

TYP.

MAX

UNIT

 

 

 

 

 

 

 

V

DC supply voltage

See Note1

1.0

3.3

5.5

V

CC

 

 

 

 

 

 

VI

Input voltage

 

0

±

VCC

V

VO

Output voltage

 

0

±

VCC

V

Tamb

Operating ambient temperature range in free

See DC and AC

±40

 

+85

°C

air

characteristics

±40

 

+125

 

 

VCC = 1.0V to 2.0V

±

±

500

 

tr, tf

Input rise and fall times

VCC = 2.0V to 2.7V

±

±

200

ns/V

VCC = 2.7V to 3.6V

±

±

100

 

 

VCC = 3.6V to 5.5V

±

±

50

 

NOTES:

1. The LV is guaranteed to function down to VCC = 1.0V (input levels GND or VCC); DC characteristics are guaranteed from VCC = 1.2V to VCC = 5.5V.

DC CHARACTERISTICS

Over operating conditions, voltages are referenced to GND (ground = 0 V)

 

 

 

 

 

LIMITS

 

 

 

 

 

 

 

 

 

 

 

 

SYMBOL

PARAMETER

TEST CONDITIONS

-40°C to +85°C

-40°C to +125°C

UNIT

 

 

 

 

 

 

 

 

 

 

 

 

MIN

TYP1

MAX

MIN

MAX

 

 

HIGH level Input

VCC = 1.2V

0.9

±

±

0.9

±

 

VIH

VCC = 2.0V

1.4

±

±

1.4

±

V

voltage

VCC = 2.7 to 3.6V

2.0

±

±

2.0

±

 

MR input

 

 

 

VCC = 4.5 to 5.5V

0.7 * VCC

±

±

0.7 * VCC

±

 

 

LOW level Input

VCC = 1.2V

±

±

0.3

±

0.3

 

VIL

VCC = 2.0V

±

±

0.6

±

0.6

V

voltage

VCC = 2.7 to 3.6V

±

±

0.8

±

0.8

 

MR input

 

 

 

VCC = 4.5 to 5.5

±

±

0.3 * VCC

±

0.3 * VCC

 

 

HIGH level Input

VCC = 1.2V

1.0

±

±

1.0

±

 

VIH

VCC = 2.0V

1.6

±

±

1.6

±

V

voltage

VCC = 2.7 to 3.6V

2.4

±

±

2.4

±

 

RS input

 

 

 

VCC = 4.5 to 5.5V

0.8 * VCC

±

±

0.8 * VCC

±

 

 

LOW level Input

VCC = 1.2V

±

±

0.2

±

0.2

 

VIL

VCC = 2.0V

±

±

0.4

±

0.4

V

voltage

VCC = 2.7 to 3.6V

±

±

0.5

±

0.5

 

RS input

 

 

 

VCC = 4.5 to 5.5

±

±

0.2 * VCC

±

0.2 * VCC

 

 

 

VCC = 1.2V; RS = GND and MR = GND;

±

±

±

±

±

 

 

 

±IO = 3.4mA

 

 

 

 

 

 

 

 

VCC = 2.0V; RS = GND and MR = GND;

±

±

±

±

±

 

 

 

±IO = 3.4mA

 

 

HIGH level output

 

 

 

 

 

 

VOH

VCC = 2.7V; RS = GND and MR = GND;

±

±

±

±

±

V

voltage;

±IO = 3.4mA

 

RTC output

 

 

 

 

 

 

 

VCC = 3.0V; RS = GND and MR = GND;

2.40

2.82

±

2.20

±

 

 

 

 

 

 

±IO = 3.4mA

 

 

 

 

 

 

 

 

VCC = 4.5V; RS = GND and MR = GND;

±

±

±

±

±

 

 

 

±IO = 3.4mA

 

 

 

 

 

 

1998 Jun 23

6

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