INTEGRATED CIRCUITS
74LV4060
14-stage binary ripple counter with oscillator
Product specification |
1998 Jun 23 |
m n r
Philips Semiconductors |
Product specification |
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14-stage binary ripple counter with oscillator |
74LV4060 |
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FEATURES
•Wide operating voltage: 1.0 to 5.5 V
•Optimized for Low Voltage applications: 1.0 to 3.6 V
•Accepts TTL input levels between VCC = 2.7 V and VCC = 3.6 V
•Typical VOLP (output ground bounce) < 0.8 V at VCC = 3.3 V, Tamb = 25 C.
•Typical VOHV (output VOH undershoot) > 2 V at VCC = 3.3 V, Tamb
= 25 C.
•All active components on chip
•RC or crystal oscillator configuration
•Output capability: standard (except for RTC and CTC)
•ICC category: MSI
QUICK REFERENCE DATA
GND = 0 V; Tamb = 25 C; tr = tf < 2.5 ns
APPLICATIONS
•Control Counters
•Timers
•Frequency Dividers
•Time-delay circuits
DESCRIPTION
The 74LV4060 is a low-voltage Si-gate CMOS device and is pin and function compatible with the 74HC/HCT4060.
The 74LV4060 is a 14-stage ripple-carry counter/divider and oscillator with three oscillator terminals (RS, RTC and CTC), ten buffered outputs (Q3 to Q9 and Q11 to Q13) and an overriding asynchronous master reset (MR). The oscillator configuration allows design of either RC or crystal oscillator circuits. The oscillator may be replaced by an external clock signal at input RS. In this case, keep the oscillator pins (RTC and CTC) floating.
The counter advances on the negative-going transition of RS. A HIGH level on MR resets the counter (Q3 to Q9 and Q11 to
Q13 = LOW), independent of the other input conditions.
SYMBOL |
PARAMETER |
CONDITIONS |
TYPICAL |
UNIT |
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Propagation delay |
CL = 15 pF |
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RS to Q3 |
VCC = 3.3 V |
29 |
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tPHL/tPLH |
Qn to Qn+1 |
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ns |
tPHL |
MR to Qn |
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fmax |
Maximum clock frequency |
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MHz |
C1 |
Input capacitance |
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3.5 |
pF |
CPD |
Power dissipation capacitance per package |
Notes 1, 2 and 3 |
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pF |
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NOTES:
1.CPD is used to determine the dynamic power
dissipation (PD in W)
PD = CPD x VCC2 x fi + (CL x VCC2 x fo) where:
fi = input frequency in MHz; CL = output load capacity in pF;
fo = output frequency in MHz; VCC = supply voltage in V;(CL x VCC2 x fo) = sum of the outputs.
2.The condition is V1 = GND to VCC
3.For formula on dynamic power dissipation, see the following pages.
ORDERING INFORMATION
PACKAGES |
TEMPERATURE RANGE |
OUTSIDE NORTH AMERICA |
NORTH AMERICA |
PKG. DWG. # |
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16-Pin Plastic DIL |
±40°C to +125°C |
74LV4060 N |
74LV4060 N |
SOT38-4 |
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16-Pin Plastic SO |
±40°C to +125°C |
74LV4060 D |
74LV4060 D |
SOT109-1 |
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16-Pin Plastic SSOP Type II |
±40°C to +125°C |
74LV4060 DB |
74LV4060 DB |
SOT338-1 |
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16-Pin Plastic TSSOP Type I |
±40°C to +125°C |
74LV4060 PW |
74LV4060PW DH |
SOT403-1 |
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1998 Jun 23 |
2 |
853-2076 19619 |
Philips Semiconductors |
Product specification |
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14-stage binary ripple counter with oscillator |
74LV4060 |
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PIN DESCRIPTION |
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LOGIC SYMBOL |
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PIN NO. |
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FUNCTION |
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1, 2, 3 |
Q11 to Q13 |
Counter outputs |
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10 |
9 |
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7, 5, 4, 6, |
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Q3 to Q9 |
Counter outputs |
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RTC CTC |
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15, 13, 15 |
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11 |
RS |
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Q3 |
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GND |
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Ground (0 V) |
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Q4 |
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5 |
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12 |
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MR |
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Q5 |
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4 |
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9 |
CTC |
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External capacitor connection |
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Q6 |
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6 |
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10 |
RTC |
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External resistor connection |
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Q7 |
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14 |
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11 |
RS |
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Clock input/oscillator pin |
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Q8 |
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Q9 |
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15 |
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MR |
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Master reset |
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Q11 |
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1 |
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16 |
VCC |
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Positive supply voltage |
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Q12 |
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2 |
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PIN CONFIGURATION |
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Q13 |
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3 |
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SV00307 |
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Q11 |
1 |
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16 |
VCC |
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Q12 |
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Q9 |
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2 |
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15 |
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Q13 |
3 |
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14 |
Q7 |
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Q8 |
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Q5 |
4 |
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13 |
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Q4 |
5 |
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MR |
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Q6 |
6 |
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11 |
RS |
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Q3 |
7 |
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10 |
RTC |
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GND |
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CTC |
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8 |
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9 |
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SV00308
LOGIC SYMBOL (IEEE/IEC)
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CTR14 |
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3 |
9 |
CX |
!G |
10 |
RX |
+ |
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11 |
RCX |
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CT |
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CT = 0 |
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9 |
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11 |
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13 |
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(a) |
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CTR14 |
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3 |
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5 |
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4 |
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4 |
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6 |
11 |
& |
+ |
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14 |
12 |
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14 |
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CT |
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13 |
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13 |
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CT = 0 |
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15 |
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15 |
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1 |
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11 |
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1 |
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2 |
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2 |
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3 |
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13 |
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3 |
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(b)
SV00311
1998 Jun 23 |
3 |
Philips Semiconductors |
Product specification |
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14-stage binary ripple counter with oscillator |
74LV4060 |
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DYNAMIC POWER DISSIPATION
GND = 0 V; Tamb = 25 C
PARAMETER |
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VCC |
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TYPICAL FORMULA FOR P |
( W)1 |
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(V) |
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D |
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1.2 |
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C |
PD |
x f |
osc |
x V |
2 + (C |
L |
x V |
CC |
2 x f |
) + 2C |
x V |
CC |
2 x f |
osc |
+ 16 x V |
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Total dynamic power dissipation when |
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CC |
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o |
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t |
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CC |
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2.0 |
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C |
PD |
x f |
osc |
x V |
2 + (C |
L |
x V |
CC |
2 x f |
) + 2C |
x V |
CC |
2 x f |
osc |
+ 460 x V |
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using the on±chip oscillator (PD) |
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CC |
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o |
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t |
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CC |
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3.0 |
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C |
PD |
x f |
osc |
x V |
2 + (C |
L |
x V |
CC |
2 x f |
) + 2C |
x V |
CC |
2 x f |
osc |
+ 1000 x V |
CC |
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CC |
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o |
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NOTE: |
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1. Where: fo = output frequency in MHz; fosc |
= oscillator frequency in MHz; |
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(C |
L |
x V |
CC |
2 |
x f ) = sum of the outputs; C |
L |
= output load capacitance in pF; |
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o |
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Ct = timing capacitance in pF; VCC = supply voltage in V.
FUNCTIONAL DIAGRAM
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10 |
9 |
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RTC |
CTC |
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RS |
CP |
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14-stage binary counter |
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CD |
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12 |
MR |
Q3 |
Q4 |
Q5 |
Q6 |
Q7 |
Q8 |
Q9 |
Q11 |
Q12 |
Q13 |
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7 |
5 |
4 |
6 |
14 |
13 |
15 |
1 |
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SV00312 |
LOGIC DIAGRAM
CTC |
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RTC |
FF4 |
FF10 |
FF12 |
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FF14 |
FF1 |
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RS |
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CP |
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Q |
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CD |
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MR |
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Q3 |
Q9 |
Q11 |
Q13 |
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SV00313 |
1998 Jun 23 |
4 |
Philips Semiconductors |
Product specification |
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14-stage binary ripple counter with oscillator |
74LV4060 |
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TIMING DIAGRAM
1 |
2 |
4 |
8 |
16 |
32 |
64 |
128 |
256 |
512 |
1.024 |
2.048 |
4.096 |
8.192 |
16.384 |
RS
MR
Q3
Q4
Q5
Q6
Q7
Q8
Q9
Q11
Q12
Q13
SV00309
ABSOLUTE MAXIMUM RATINGS1, 2
In accordance with the Absolute Maximum Rating System (IEC 134)
Voltages are referenced to GND (ground = 0V)
SYMBOL |
PARAMETER |
CONDITIONS |
RATING |
UNIT |
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VCC |
DC supply voltage |
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±0.5 to +7.0 |
V |
±IIK |
DC input diode current |
VI < ±0.5 or VI > VCC + 0.5V |
20 |
mA |
±IOK |
DC output diode current |
VO < ±0.5 or VO > VCC + 0.5V |
50 |
mA |
±IO |
DC output source or sink current |
±0.5V < VO < VCC + 0.5V |
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± standard outputs |
25 |
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±IGND, |
DC VCC or GND current for types with |
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mA |
±standard outputs |
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50 |
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±ICC |
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Tstg |
Storage temperature range |
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±65 to +150 |
°C |
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Power dissipation per package |
for temperature range: ±40 to +125°C |
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PTOT |
±plastic DIL |
above +70°C derate linearly with 12mW/K |
750 |
mW |
±plastic mini-pack (SO) |
above +70°C derate linearly with 8 mW/K |
500 |
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±plastic shrink mini-pack (SSOP and TSSOP) |
above +60°C derate linearly with 5.5 mW/K |
400 |
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NOTES:
1.Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under ªrecommended operating conditionsº is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
2.The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
1998 Jun 23 |
5 |
Philips Semiconductors |
Product specification |
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14-stage binary ripple counter with oscillator |
74LV4060 |
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RECOMMENDED OPERATING CONDITIONS
SYMBOL |
PARAMETER |
CONDITIONS |
MIN |
TYP. |
MAX |
UNIT |
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V |
DC supply voltage |
See Note1 |
1.0 |
3.3 |
5.5 |
V |
CC |
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VI |
Input voltage |
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0 |
± |
VCC |
V |
VO |
Output voltage |
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0 |
± |
VCC |
V |
Tamb |
Operating ambient temperature range in free |
See DC and AC |
±40 |
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+85 |
°C |
air |
characteristics |
±40 |
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+125 |
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VCC = 1.0V to 2.0V |
± |
± |
500 |
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tr, tf |
Input rise and fall times |
VCC = 2.0V to 2.7V |
± |
± |
200 |
ns/V |
VCC = 2.7V to 3.6V |
± |
± |
100 |
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VCC = 3.6V to 5.5V |
± |
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50 |
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NOTES:
1. The LV is guaranteed to function down to VCC = 1.0V (input levels GND or VCC); DC characteristics are guaranteed from VCC = 1.2V to VCC = 5.5V.
DC CHARACTERISTICS
Over operating conditions, voltages are referenced to GND (ground = 0 V)
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LIMITS |
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SYMBOL |
PARAMETER |
TEST CONDITIONS |
-40°C to +85°C |
-40°C to +125°C |
UNIT |
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MIN |
TYP1 |
MAX |
MIN |
MAX |
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HIGH level Input |
VCC = 1.2V |
0.9 |
± |
± |
0.9 |
± |
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VIH |
VCC = 2.0V |
1.4 |
± |
± |
1.4 |
± |
V |
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voltage |
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VCC = 2.7 to 3.6V |
2.0 |
± |
± |
2.0 |
± |
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MR input |
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VCC = 4.5 to 5.5V |
0.7 * VCC |
± |
± |
0.7 * VCC |
± |
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LOW level Input |
VCC = 1.2V |
± |
± |
0.3 |
± |
0.3 |
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VIL |
VCC = 2.0V |
± |
± |
0.6 |
± |
0.6 |
V |
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voltage |
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VCC = 2.7 to 3.6V |
± |
± |
0.8 |
± |
0.8 |
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MR input |
|
|||||||
|
|
VCC = 4.5 to 5.5 |
± |
± |
0.3 * VCC |
± |
0.3 * VCC |
|
|
|
HIGH level Input |
VCC = 1.2V |
1.0 |
± |
± |
1.0 |
± |
|
|
VIH |
VCC = 2.0V |
1.6 |
± |
± |
1.6 |
± |
V |
||
voltage |
|||||||||
VCC = 2.7 to 3.6V |
2.4 |
± |
± |
2.4 |
± |
||||
|
RS input |
|
|||||||
|
|
VCC = 4.5 to 5.5V |
0.8 * VCC |
± |
± |
0.8 * VCC |
± |
|
|
|
LOW level Input |
VCC = 1.2V |
± |
± |
0.2 |
± |
0.2 |
|
|
VIL |
VCC = 2.0V |
± |
± |
0.4 |
± |
0.4 |
V |
||
voltage |
|||||||||
VCC = 2.7 to 3.6V |
± |
± |
0.5 |
± |
0.5 |
||||
|
RS input |
|
|||||||
|
|
VCC = 4.5 to 5.5 |
± |
± |
0.2 * VCC |
± |
0.2 * VCC |
|
|
|
|
VCC = 1.2V; RS = GND and MR = GND; |
± |
± |
± |
± |
± |
|
|
|
|
±IO = 3.4mA |
|
|
|
|
|
|
|
|
|
VCC = 2.0V; RS = GND and MR = GND; |
± |
± |
± |
± |
± |
|
|
|
|
±IO = 3.4mA |
|
||||||
|
HIGH level output |
|
|
|
|
|
|
||
VOH |
VCC = 2.7V; RS = GND and MR = GND; |
± |
± |
± |
± |
± |
V |
||
voltage; |
|||||||||
±IO = 3.4mA |
|||||||||
|
RTC output |
|
|
|
|
|
|
||
|
VCC = 3.0V; RS = GND and MR = GND; |
2.40 |
2.82 |
± |
2.20 |
± |
|
||
|
|
|
|||||||
|
|
±IO = 3.4mA |
|
|
|
|
|
|
|
|
|
VCC = 4.5V; RS = GND and MR = GND; |
± |
± |
± |
± |
± |
|
|
|
|
±IO = 3.4mA |
|
|
|
|
|
|
1998 Jun 23 |
6 |