Philips 74lv4052 DATASHEETS
INTEGRATED CIRCUITS
74LV4052
Dual 4-channel analog
multiplexer/demultiplexer
Product specification
Supersedes data of 1997 Jul 15
IC24 Data Handbook
1998 Jun 23
Philips Semiconductors Product specification
ns
F
74L V4052Dual 4-channel analog multiplexer/demultiplexer
FEA TURES
•Optimized for low voltage applications: 1.0 to 6.0 V
•Accepts TTL input levels between V
= 2.7 V and V
CC
CC
= 3.6 V
•Low typ “ON” resistance:
60 at V
90 at V
145 at Vcc – VEE = 2.0 V
– VEE = 4.5 V
cc
– VEE = 3.0 V
cc
•Logic level translation: to enable 3 V logic to communicate with ± 3
V analog signals
•Typical “break before make” built in
•Analog/Digital multiplexing and demultiplexing
•Signal gating
•Output capability: non-standard
•I
category: MSI
CC
DESCRIPTION
The 74LV4052 is a low-voltage CMOS device and is pin and
function compatible with the 74HC/HCT4052.
The 74LV4052 is a dual 4-channel analog multiplexer/demultiplexer
with a common select logic. Each multiplexer has four independent
inputs/outputs (nY
common channel select logics include two digital select inputs (S
and S1) and an active LOW enable input (E).
With E
LOW, one of the four switches is selected (low impedance
ON-state) by S
impedance OFF-state, independent of S
the supply voltage pins for the digital control inputs (S
The V
(nY
V
to GND ranges are 1.0 to 6.0 V. The analog inputs/outputs
CC
, to nY3, and nZ) can swing between VCC as a positive limit and
0
as a negative limit. VCC - VEE may not exceed 6.0 V. For
EE
operation as a digital multiplexer/demultiplexer, V
GND (typically ground).
to nY3) and a common input/output (nZ). The
0
and S1. With E HIGH, all switches are in the high
0
and S1. VCC and GND are
0
, S1 and E).
0
is connected to
EE
QUICK REFERENCE DATA
GND = 0 V; T
= 25°C; tr =t
amb
SYMBOL PARAMETER CONDITIONS TYPICAL UNIT
t
PZH/tPZL
t
PHZ/tPLZ
C
I
C
PD
C
S
Turn “ON” time
E or V
OS
Turn “OFF” time
E or V
OS
Input capacitance 3.5
Power dissipation capacitance per switch See Notes 1 and 2 57
Maximum switch capacitance
independent (Y) common (Z)
NOTES:
is used to determine the dynamic power dissipation (PD in µW)
1. C
PD
= CPD × V
P
D
f
= input frequency in MHz; CL = output load capacity in pF;
i
f
= output frequency in MHz; CS = maximum switch capacitance in pF;
o
= supply voltage in V;
V
CC
+CS) × V
((C
L
2. The condition is V
2
× fi ((C
CC
CC
I
≤ 2.5 ns
f
S
n
S
n
CS) × V
L +
2
× fo) = sum of the outputs.
CC
= GND to VCC.
2
× fo) where:
CL = 15 pF
R
= 1K
L
VCC = 3.3 V
30
22
5
12
0
p
ORDERING INFORMATION
PACKAGES TEMPERATURE RANGE OUTSIDE NORTH AMERICA NORTH AMERICA Code
16-Pin Plastic DIL –40°C to +125°C 74LV4052 N 74LV4052 N SOT38-4
16-Pin Plastic SO –40°C to +125°C 74LV4052 D 74LV4052 D SOT109-1
16-Pin Plastic SSOP Type II –40°C to +125°C 74LV4052 DB 74LV4052 DB SOT338-1
16-Pin Plastic TSSOP Type I –40°C to +125°C 74LV4052 PW 74LV4052PW DH SOT403-1
PIN CONFIGURATION
1998 Jun 23 853-1999 19618
2Y
2Y
2Y
2Y
V
GND
PIN DESCRIPTION
1
0
2
2
2Z
3
4
3
5
1
E
6
7
EE
8
16
15
14
13
12
11
10
9
SV01697
V
CC
1Y
2
1Y
1
1Z
1Y
0
1Y
3
S
0
S
1
PIN NUMBER SYMBOL FUNCTION
1, 5, 2, 4 2Y0, 2Y
Independent inputs/outputs
3
6 E Enable input (active LOW)
7 V
EE
Negative supply voltage
8 GND Ground (0 V)
10, 9 S0, S
1
Select inputs
12, 14, 15, 11 1Y0 to 1Y3Independent inputs/outputs
13, 3 1Z, 2Z Common inputs/outputs
16 V
CC
Positive supply voltage
2
Philips Semiconductors Product specification
Dual 4-channel analog multiplexer/demultiplexer
LOGIC SYMBOL
LOGIC SYMBOL (IEEE/IEC)
10
9
6
FUNCTION TABLE
13
1Z
1Y
S
0
1Y
1Y
S
1
1Y
2Y
2Y
2Y
2Y
E
2Z
3
0
1
2
3
0
1
2
3
SV01698
12
14
15
11
1
5
2
4
74LV4052
10
0
0
1
G4
4X
MDX
3
1
0
5
1
2
2
4
3
12
14
15
11
9
6
3
13
INPUTS
E S
1
S
0
L L L nY0 – nZ
L L H nY1 – nZ
L H L nY2 – nZ
L H H nY3 – nZ
H X X None
NOTES:
1. H = HIGH voltage level
2. L = LOW voltage level
3. X = don’t care
CHANNEL
ON
SV01699
1998 Jun 23
3
Philips Semiconductors Product specification
Dual 4-channel analog multiplexer/demultiplexer
FUNCTIONAL DIAGRAM
16
V
CC
10
S
0
9
S
1
LOGIC LEVEL
CONVERSION
1–of–4
DECODER
74LV4052
13
1Z
1Y
0
12
1Y
14
1
1Y
15
2
1Y
3
11
2Y
0
1
6
E
SCHEMATIC DIAGRAM (ONE SWITCH)
from logic
GND
8
2Y
2Y
2Y
V
EE
7
V
CC
V
EE
1
2
3
2Z
SV01700
V
CC
V
CC
5
2
4
3
Y
V
EE
V
CC
V
EE
Z
1998 Jun 23
SV01695
4
Philips Semiconductors Product specification
Dual 4-channel analog multiplexer/demultiplexer
ABSOLUTE MAXIMUM RATINGS
1, 2
74LV4052
In accordance with the Absolute Maximum Rating System (IEC 134).
Voltages are referenced to GND (ground = 0 V).
SYMBOL
V
CC
I
IK
I
SK
I
S
T
stg
P
TOT
DC supply voltage –0.5 to +7.0 V
DC input diode current VI < –0.5 or VI > VCC + 0.5 V 20 mA
DC switch diode current VS < –0.5 or VS > VCC + 0.5 V 20 mA
DC switch current –0.5 V < VS < VCC + 0.5 V 25 mA
Storage temperature range –65 to +150 °C
Power dissipation per package
– plastic DIL
– plastic mini-pack (SO)
– plastic shrink mini-pack (SSOP and TSSOP)
PARAMETER CONDITIONS RATING UNIT
for temperature range: –40 to +125°C
above +70°C derate linearly with 12 mW/K
above +70°C derate linearly with 8 mW/K
above +60°C derate linearly with 5.5 mW/K
750
500
400
mW
NOTES:
1. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the
device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to
absolute-maximum-rated conditions for extended periods may affect device reliability .
2. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
RECOMMENDED OPERATING CONDITIONS
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNIT
V
V
V
T
amb
tr, t
NOTE:
1. The LV is guaranteed to function down to V
DC supply voltage See Note 1 and Figure 5 1.0 3.3 6.0 V
CC
Input voltage 0 – V
I
Output voltage 0 – V
O
Operating ambient temperature range in free air
Input rise and fall times
f
= 1.0V (input levels GND or VCC); DC characteristics are guaranteed from VCC = 1.2V to VCC = 6.0V .
CC
See DC and AC
characteristics
VCC = 1.0 V to 2.0 V
VCC = 2.0 V to 2.7 V
VCC = 2.7 V to 6.0 V
–40
–40
–
–
–
–
–
–
CC
CC
+85
+125
500
200
100
°C
ns/V
V
V
1998 Jun 23
5
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