Philips 74lv4040 DATASHEETS

INTEGRATED CIRCUITS

74LV4040

12-stage binary ripple counter

Product specification 1998 Jun 23 IC24 Data Handbook

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Philips Semiconductors Product specification

74L V404012-stage binary ripple counter

FEA TURES

•Optimized for Low Voltage applications: 1.0 to 5.5V

•Accepts TTL input levels between V

•Typical V

T

amb

•Typical V

T

amb

(output ground bounce)  0.8V @ VCC = 3.3V,

OLP

= 25°C

(output VOH undershoot)  2V @ VCC = 3.3V,

OHV

= 25°C

= 2.7V and VCC = 3.6V

CC

•Frequency dividing circuits

•Time delay circuits

•Control counters

•Output capability: standard

•I

category: MSI

CC

QUICK REFERENCE DATA

GND = 0V; T

SYMBOL

t

PHL/tPLH

f

max

C

I

C

PD

NOTES:

is used to determine the dynamic power dissipation (PD in µW)

1. C

PD

= CPD  V

P

D

f

= input frequency in MHz; CL = output load capacity in pF;

i

= output frequency in MHz; VCC = supply voltage in V;

f

o

 (C

2. The condition is V

= 25°C; tr =tf 2.5 ns

amb

CC

2

 V

L

 fo) = sum of the outputs.

CC

PARAMETER CONDITIONS TYPICAL UNIT

Propagation delay CP to Q

0

Qn to Q

n+1

MR to Q

n

Maximum clock frequency 100 MHz Input capacitance 3.5 pF Power dissipation capacitance per gate

2

x fi  (CL  V

= GND to V

I

CC

2

 fo) where:

CC

DESCRIPTION

The 74LV4040 is a low–voltage Si–gate CMOS device and is pin and function compatible with 74HC/HCT4040.

The 74LV4040 is a 12-stage binary ripple counter with a click input (CP

), an overriding asynchronous master reset input (MR) and twelve fully buffered parallel outputs (Q advanced on the HIGH-to-LOW transition of CP clears all counter stages and forces all outputs LOW, independent of the state of CP

Each counter stage is a static toggle flip-flop.

CL = 15pF VCC = 3.3V

Notes 1 and 2

.

to Q11). The counter is

0

. A HIGH on MR

12

7

16

30 pF

ns

ORDERING INFORMATION

PACKAGES TEMPERATURE RANGE OUTSIDE NORTH AMERICA NORTH AMERICA PKG. DWG. #

16-Pin Plastic DIL –40°C to +125°C 74LV4040 N 74LV4040 N SOT38-4 16-Pin Plastic SO –40°C to +125°C 74LV4040 D 74LV4040 D SOT109-1 16-Pin Plastic SSOP Type II –40°C to +125°C 74LV4040 DB 74LV4040 DB SOT338-1 16-Pin Plastic TSSOP Type I –40°C to +125°C 74LV4040 PW 74LV4040PW DH SOT403-1

1998 Jun 23 853-2075 19619

2

Philips Semiconductors Product specification

74LV404012-stage binary ripple counter

PIN CONFIGURATION

16

Q

GND

1

11

2

Q

5

3

Q

4

Q

6

5

Q

3

6

Q

2

Q

7

1

8

V

15

Q

14 13

Q Q

12 11

MR CP

10 9

Q

SV00316

CC

10 9 7 8

0

Figure 1. Pin configuration

PIN DESCRIPTION

NUMBER

9, 7, 6, 5, 3, 2, 4, 13, 12, 14, 15, 1

8 GND Ground (0V) 10 CP 11 MR Master reset input (active HIGH)

16 V

SYMBOL FUNCTION

Q0 to Q

Parallel outputs

11

Clock input (HIGH-to-LOW, edgetriggered)

CC

Positive supply voltage

LOGIC SYMBOL

10

11

CP

MR

Figure 3. Logic symbol

FUNCTIONAL DIAGRAM

CP

T

11

MR

C

D

Q

1

0

7109

12-STAGE COUNTER

Q3Q

2

9

Q

0

7

Q

1

6

Q

2

5

Q

3

Q

4

2

Q

5

4

Q

6

13

Q

7

12

Q

8

14

Q

9

15

Q

10

1

Q

11

SV00317

Q

4

5

Q8Q7Q6Q

Q9Q10Q 14 1512 11352543

11

LOGIC SYMBOL (IEEE/IEC)

CTR12

10 11

+ CT=0

CT

Figure 2. IEC Logic symbol

0

11

9 7 5 5 3

2 4 13 12 14 15

1

SV00318

Figure 4. Functional diagram

LOGIC DIAGRAM

CP

MR

SV00319

FF0 FF3 FF11

QQQ

T

Q

R

D

TT

Q Q

R

D

Q0

Q1 Q11

R

D

SV00320

Figure 5. Logic diagram

1998 Jun 23

3

Philips Semiconductors Product specification

74LV404012-stage binary ripple counter

4.0962.0481.0245122561286432168421

CP INPUT

MR INPUT

OUTPUT

Q

0

OUTPUT

Q

1

Q

OUTPUT

2

Q

OUTPUT

3

OUTPUT

Q

4

Q

OUTPUT

5

Q

OUTPUT

6

Q7 OUTPUT

OUTPUT

Q

8

Q

OUTPUT

9

Q10 OUTPUT

Q

OUTPUT

11

FUNCTION TABLE

INPUTS OUTPUTS

CP MR Q0, Q3 to Q

 L no change  L count

X H L

NOTES:

H = HIGH voltage level L = LOW voltage level X = Don’t care

 = LOW -to-HIGH clock transition  = HIGH-to-LOW clock transition

SV00310

Figure 6. Timing diagram

13

1998 Jun 23

4

Philips Semiconductors Product specification

74LV404012-stage binary ripple counter

ABSOLUTE MAXIMUM RATINGS

1, 2

In accordance with the Absolute Maximum Rating System (IEC 134) Voltages are referenced to GND (ground = 0V)

SYMBOL

V

CC

±I

IK

±I

OK

±I

O

±I

GND

±I

CC

T

stg

P

TOT

DC supply voltage –0.5 to +7.0 V DC input diode current VI < –0.5 or VI > VCC + 0.5V 20 mA DC output diode current VO < –0.5 or VO > VCC + 0.5V 50 mA DC output source or sink current

– standard outputs DC VCC or GND current for types with

,

–standard outputs 50 Storage temperature range –65 to +150 °C

Power dissipation per package –plastic DIL –plastic mini-pack (SO) –plastic shrink mini-pack (SSOP and TSSOP)

PARAMETER CONDITIONS RATING UNIT

–0.5V < VO < VCC + 0.5V

25

mA

for temperature range: –40 to +125°C above +70°C derate linearly with 12mW/K above +70°C derate linearly with 8 mW/K above +60°C derate linearly with 5.5 mW/K

750 500 400

mW

NOTES:

1. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability .

2. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.

RECOMMENDED OPERATING CONDITIONS

SYMBOL PARAMETER CONDITIONS MIN TYP. MAX UNIT

1

1.0 3.3 5.5 V

CC CC

–40 –40

– – – –

+85

+125

500 200 100

50

ns/V

V V

°C

T

V

tr, t

CC

V

amb

DC supply voltage See Note Input voltage 0 – V

I

Output voltage 0 – V

O

Operating ambient temperature range in free air

Input rise and fall times

f

NOTE:

1. The LV is guaranteed to function down to V

See DC and AC characteristics

VCC = 1.0V to 2.0V VCC = 2.0V to 2.7V V

= 2.7V to 3.6V

CC

VCC = 3.6V to 5.5V

= 1.0V (input levels GND or VCC); DC characteristics are guaranteed from VCC = 1.2V to VCC = 5.5V.

CC

1998 Jun 23

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