INTEGRATED CIRCUITS
74LV393
Dual 4-bit binary ripple counter
Product specification |
1997 Jun 10 |
Supersedes data of 1997 Mar 04
IC24 Data Handbook
m n r
Philips Semiconductors |
Product specification |
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Dual 4-bit binary ripple counter |
74LV393 |
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FEATURES
•Optimized for Low Voltage applications: 1.0 to 3.6V
•Accepts TTL input levels between VCC = 2.7V and VCC = 3.6V
•Typical VOLP (output ground bounce) 0.8V @ VCC = 3.3V,
Tamb = 25°C
•Typical VOHV (output VOH undershoot) 2V @ VCC = 3.3V, Tamb = 25°C
•Two 4-bit binary counters with individual clocks
•Divide-by any binary module up to 28 in one package
•Two master resets to clear each 4-bit counter individually
•Output capability: standard
•ICC category: MSI
DESCRIPTION
The 74LV393 is a low±voltage Si-gate CMOS device and is pin and function compatible with 74HC/HCT393.
The 74LV393 is a dual 4-bit binary ripple counter with separate clocks (1CP, 2CP) and master reset (1MR, 2MR) inputs to each counter.
The operation of each half of the ``393'' is the same as the ``93'' except no external clock connections are required. The counters are triggered by a HIGH-to-LOW transition of the clock inputs. The counter outputs are internally connected to provide clock inputs to succeeding stages. The outputs of the ripple counter do not change synchronously and should not be used for high-speed address decoding.
The master resets are active-HIGH asynchronous inputs to each 4-bit counter identified by the ``1'' and ``2'' in the pin description.
A HIGH level on the nMR input overrides the clock and sets the outputs LOW.
QUICK REFERENCE DATA
GND = 0V; Tamb = 25°C; tr = tf 2.5 ns
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PARAMETER |
CONDITIONS |
TYPICAL |
UNIT |
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Propagation delay |
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to nQ0 |
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12 |
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tPHL/tPLH |
nCP |
CL = 15pF |
ns |
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nQ to nQn+1 |
4 |
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nMR to nQn |
VCC = 3.3V |
11 |
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fmax |
Maximum clock frequency |
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99 |
MHz |
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CI |
Input capacitance |
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3.5 |
pF |
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CPD |
Power dissipation capacitance per flip-flop |
VI = GND to VCC 1 |
23 |
pF |
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NOTE:
1.CPD is used to determine the dynamic power dissipation (PD in μW) PD = CPD VCC2 fi (CL VCC2 fo) where:
fi = input frequency in MHz; CL = output load capacity in pF;
fo = output frequency in MHz; VCC = supply voltage in V;
(CL VCC2 fo) = sum of the outputs.
ORDERING INFORMATION
PACKAGES |
TEMPERATURE RANGE |
OUTSIDE NORTH AMERICA |
NORTH AMERICA |
PKG. DWG. # |
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14-Pin Plastic DIL |
±40°C to +125°C |
74LV393 N |
74LV393 N |
SOT27-1 |
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14-Pin Plastic SO |
±40°C to +125°C |
74LV393 D |
74LV393 D |
SOT108-1 |
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14-Pin Plastic SSOP Type II |
±40°C to +125°C |
74LV393 DB |
74LV393 DB |
SOT337-1 |
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14-Pin Plastic TSSOP Type I |
±40°C to +125°C |
74LV393 PW |
74LV393PW DH |
SOT402-1 |
PIN CONFIGURATION |
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PIN DESCRIPTION |
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VCC |
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PIN |
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SYMBOL |
FUNCTION |
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1CP |
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1 |
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14 |
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NUMBER |
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1MR |
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2 |
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13 |
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2CP |
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Clock inputs |
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1, 13 |
1CP, 2CP |
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(HIGH-to-LOW, edge-triggered) |
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1Q0 |
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3 |
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12 |
2MR |
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2Q0 |
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2, 12 |
1MR, 2MR |
Asynchronous master reset inputs |
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1Q1 |
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4 |
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11 |
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(active HIGH) |
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2Q1 |
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1Q2 |
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5 |
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10 |
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3, 4, 5, 6 |
1Q0 to 1Q3 |
Flip-flop outputs |
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1Q3 |
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6 |
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9 |
2Q2 |
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11, 10, 9, 8 |
2Q0 to 2Q3 |
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GND |
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2Q3 |
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7 |
GND |
Ground (0V) |
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7 |
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8 |
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SV00672 |
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14 |
VCC |
Positive supply voltage |
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1998 Jun 10 |
2 |
853±1936 19545 |
Philips Semiconductors |
Product specification |
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Dual 4-bit binary ripple counter |
74LV393 |
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LOGIC SYMBOL |
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FUNCTIONAL DIAGRAM |
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1 |
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1Q0 |
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1CP |
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3 |
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1 |
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1CP |
1Q0 |
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3 |
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4±BIT |
1Q1 |
4 |
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BINARY |
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1 |
1Q1 |
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4 |
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1Q2 |
5 |
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RIPPLE |
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1Q2 |
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5 |
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2 |
1MR |
COUNTER |
1Q3 |
6 |
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2 |
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1MR |
1Q3 |
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6 |
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13 |
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2Q0 |
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2CP |
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11 |
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13 |
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2CP |
2Q0 |
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11 |
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4±BIT |
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2Q1 |
10 |
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BINARY |
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2Q1 |
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10 |
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2Q2 |
9 |
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2 |
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RIPPLE |
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2Q2 |
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9 |
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12 |
2MR |
COUNTER |
2Q3 |
8 |
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12 |
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2MR |
2Q3 |
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8 |
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SV00673 |
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SV00675 |
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LOGIC SYMBOL (IEEE/IEC)
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CTR4 |
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0 |
3 |
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2 |
CT=0 |
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4 |
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1 |
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CT |
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+ |
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3 |
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CTR4 |
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0 |
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11 |
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12 |
CT=0 |
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10 |
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13 |
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CT |
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+ |
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3 |
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SV00674 |
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STATE DIAGRAM
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0 |
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2 |
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15 |
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14 |
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6 |
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13 |
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7 |
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12 |
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10 |
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9 |
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SV00676 |
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COUNT SEQUENCE FOR 1 COUNTER |
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COUNT |
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OUTPUTS |
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Q0 |
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Q1 |
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Q2 |
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Q3 |
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0 |
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L |
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L |
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L |
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L |
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1 |
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H |
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L |
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L |
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2 |
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H |
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3 |
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4 |
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5 |
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6 |
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7 |
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8 |
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10 |
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11 |
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12 |
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13 |
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14 |
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L |
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15 |
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H |
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H |
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1998 Jun 10 |
3 |
Philips Semiconductors |
Product specification |
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Dual 4-bit binary ripple counter |
74LV393 |
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LOGIC DIAGRAM
|
Q |
Q |
Q |
Q |
CP |
T FF1 |
T FF2 |
T FF3 |
T FF4 |
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RD |
RD |
RD |
RD |
MR |
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Q0 |
Q1 |
Q2 |
Q3 |
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SV00677 |
RECOMMENDED OPERATING CONDITIONS
SYMBOL |
PARAMETER |
CONDITIONS |
MIN |
TYP |
MAX |
UNIT |
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VCC |
DC supply voltage |
See Note 1 |
1.0 |
3.3 |
3.6 |
V |
VI |
Input voltage |
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0 |
± |
VCC |
V |
VO |
Output voltage |
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0 |
± |
VCC |
V |
Tamb |
Operating ambient temperature range in free |
See DC and AC |
±40 |
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+85 |
°C |
air |
characteristics |
±40 |
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+125 |
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VCC = 1.0V to 2.0V |
± |
± |
500 |
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tr, tf |
Input rise and fall times |
VCC = 2.0V to 2.7V |
± |
± |
200 |
ns/V |
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VCC = 2.7V to 3.6V |
± |
± |
100 |
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NOTES:
1. The LV is guaranteed to function down to VCC = 1.0V (input levels GND or VCC); DC characteristics are guaranteed from VCC = 1.2V to VCC =3.6V.
ABSOLUTE MAXIMUM RATINGS1, 2
In accordance with the Absolute Maximum Rating System (IEC 134).
Voltages are referenced to GND (ground = 0V).
SYMBOL |
PARAMETER |
CONDITIONS |
RATING |
UNIT |
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VCC |
DC supply voltage |
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±0.5 to +4.6 |
V |
±IIK |
DC input diode current |
VI < ±0.5 or VI > VCC + 0.5V |
20 |
mA |
±IOK |
DC output diode current |
VO < ±0.5 or VO > VCC + 0.5V |
50 |
mA |
±IO |
DC output source or sink current |
±0.5V < VO < VCC + 0.5V |
25 |
mA |
± standard outputs |
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±IGND, |
DC VCC or GND current for types with |
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50 |
mA |
± standard outputs |
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±ICC |
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Tstg |
Storage temperature range |
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±65 to +150 |
°C |
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Power dissipation per package |
for temperature range: ±40 to +125°C |
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PTOT |
± plastic DIL |
above +70°C derate linearly with 12 mW/K |
750 |
mW |
± plastic mini-pack (SO) |
above +70°C derate linearly with 8 mW/K |
500 |
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± plastic shrink mini-pack (SSOP and TSSOP) |
above +60°C derate linearly with 5.5 mW/K |
400 |
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NOTES:
1.Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under ªrecommended operating conditionsº is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
2.The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
1998 Jun 10 |
4 |
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