Philips 74LV377PW, 74LV377N, 74LV377DB, 74LV377D Datasheet

INTEGRATED CIRCUITS

74LV377

Octal D-type flip-flop with data enable; positive edge-trigger

Product specification

1998 Jun 10

Supersedes data of 1997 Mar 04

IC24 Data Handbook

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	Philips Semiconductors	Product specification
	Octal D-type flip-flop with data enable;	74LV377
	positive edge-trigger

FEATURES

•Optimized for Low Voltage applications: 1.0 to 3.6V

•Accepts TTL input levels between VCC = 2.7V and VCC = 3.6V

•Typical VOLP (output ground bounce) 0.8V @ VCC = 3.3V,

Tamb = 25°C

•Typical VOHV (output VOH undershoot) 2V @ VCC = 3.3V, Tamb = 25°C

•Ideal for addressable register applications

•Data enable for address and data synchronization applications

•Eight positive-edge triggered D-type flip-flops

•Output capability: standard

•ICC category: MSI

DESCRIPTION

The 74LV377 is a low±voltage CMOS device and is pin and function compatible with 74HC/HCT377.

The 74LV377 has eight edge-triggered, D-type flip-flops with individual D inputs and Q outputs. A common clock (CP) input loads

all flip-flops simultaneously when the data enable (E) is LOW. The state of each D input, one set-up time before the LOW-to-HIGH clock transition, is transferred to the corresponding output (Qn) of

the flip-flop. The E input must be stable only one set-up time prior to the LOW-to-HIGH transition for predictable operation.

QUICK REFERENCE DATA

GND = 0V; Tamb = 25°C; tr = tf 2.5 ns

	SYMBOL	PARAMETER	CONDITIONS	TYPICAL	UNIT
	tPHL/tPLH	Propagation delay		13	ns
		CP to Qn	CL = 15pF
			VCC = 3.3V
	fmax	Maximum clock frequency		77	MHz
	CI	Input capacitance		3.5	pF
	CPD	Power dissipation capacitance per flip-flop	Notes 1 and 2	20	pF

NOTES:

1.CPD is used to determine the dynamic power dissipation (PD in mW)

PD = CPD VCC2 fi (CL VCC2 fo) where:

fi = input frequency in MHz; CL = output load capacity in pF;

fo = output frequency in MHz; VCC = supply voltage in V;

(CL VCC2 fo) = sum of the outputs.

2.The condition is VI = GND to VCC

ORDERING INFORMATION

PACKAGES	TEMPERATURE RANGE	OUTSIDE NORTH AMERICA	NORTH AMERICA	PKG. DWG. #
20-Pin Plastic DIL	±40°C to +125°C	74LV377 N	74LV377 N	SOT146-1
20-Pin Plastic SO	±40°C to +125°C	74LV377 D	74LV377 D	SOT163-1
20-Pin Plastic SSOP Type II	±40°C to +125°C	74LV377 DB	74LV377 DB	SOT339-1
20-Pin Plastic TSSOP Type I	±40°C to +125°C	74LV377 PW	74LV377PW DH	SOT360-1

PIN DESCRIPTION

	PIN	SYMBOL			FUNCTION
	NUMBER
	1				Data enable input (active-LOW)
			E
	2, 5, 6, 9, 12,	Q0 to Q7			flip-flop outputs
	15, 16, 19
	3, 4, 7, 8, 13,	D0 to D7			Data inputs
	14, 17, 18
	10	GND			Ground (0V)
	11	CP			Clock input
					(LOW-to-HIGH, edge-triggered)
	20	VCC			Positive supply voltage

FUNCTION TABLE

	OPERATING MODES			INPUTS					OUTPUTS
			CP			E		Dn	Qn
	Load ``1''		↑			l		h	H
	Load ``0''		↑			l		l	L
	Hold (do nothing)		↑			h		X	No change
			X		H			X	No change
H	= HIGH voltage level

h= HIGH voltage level one set-up time prior to the

LOW-to-HIGH CP transition

L	=	LOW voltage level
l	= LOW voltage level one set-up time prior to the
↑		LOW-to-HIGH CP transition
	=	LOW±to±HIGH CP transition
X	=	Don't care

1998 Jun 10

2

853±1935 19545

Philips Semiconductors	Product specification

Octal D-type flip-flop with data enable;

74LV377

positive edge-trigger

PIN CONFIGURATION								LOGIC SYMBOL (IEEE/IEC)
								11
									1C2
								1
E			1		20	VCC			G1
						Q7
Q0			2		19			3				2
D0			3		18	D7			2D
D1			4		17	D6		4				5
Q1			5		16	Q6		7				6
Q2			6		15	Q5		8				9
D2			7		14	D5		13				12
D3			8		13	D4		14				15
Q3			9		12	Q4		17				16
GND			10		11	CP		18				19
					SV00667
												SV00669
LOGIC SYMBOL								FUNCTIONAL DIAGRAM

				11
3		D0	CP			2
				Q0
4		D1		Q1		5
7		D2		Q2		6
8		D3		Q3		9
13		D4		Q4		12
14		D5		Q5		15
17		D6		Q6		16
18		D7		Q7		19
			E
				1

D0			Q0	2
3
D1			Q1	5
4
D2			Q2	6
7
D3			Q3	9
8	FF1
D4	to	OUTPUTS	Q4	12
13	FF8
D5			Q5	15
14
D6			Q6	16
17
D7			Q7	19
18
E
1
CP
11

SV00668

SV00670

1998 Jun 10

3

Philips Semiconductors	Product specification

Octal D-type flip-flop with data enable;

74LV377

positive edge-trigger

RECOMMENDED OPERATING CONDITIONS

SYMBOL	PARAMETER	CONDITIONS	MIN	TYP	MAX	UNIT
VCC	DC supply voltage	See Note 1	1.0	3.3	3.6	V
VI	Input voltage		0	±	VCC	V
VO	Output voltage		0	±	VCC	V
Tamb	Operating ambient temperature range in free air	See DC and AC	±40		+85	°C
		characteristics	±40		+125
		VCC = 1.0V to 2.0V	±	±	500
				±
tr, tf	Input rise and fall times	VCC = 2.0V to 2.7V	±	±	200	ns/V
		VCC = 2.7V to 3.6V	±	±	100

NOTE:

1. The LV is guaranteed to function down to VCC = 1.0V (input levels GND or VCC); DC characteristics are guaranteed from VCC = 1.2V to VCC = 3.6V.

ABSOLUTE MAXIMUM RATINGS1, 2

In accordance with the Absolute Maximum Rating System (IEC 134).

Voltages are referenced to GND (ground = 0V).

SYMBOL	PARAMETER	CONDITIONS	RATING	UNIT
VCC	DC supply voltage		±0.5 to +4.6	V
±IIK	DC input diode current	VI < ±0.5 or VI > VCC + 0.5V	20	mA
±IOK	DC output diode current	VO < ±0.5 or VO > VCC + 0.5V	50	mA
±IO	DC output source or sink current	±0.5V < VO < VCC + 0.5V	25	mA
	± standard outputs
±IGND,	DC VCC or GND current for types with		50	mA
	±standard outputs
±ICC
Tstg	Storage temperature range		±65 to +150	°C
	Power dissipation per package	for temperature range: ±40 to +125°C
Ptot	±plastic DIL	above +70°C derate linearly with 12mW/K	750	mW
	±plastic mini-pack (SO)	above +70°C derate linearly with 8 mW/K	500
	±plastic shrink mini-pack (SSOP and TSSOP)	above +60°C derate linearly with 5.5 mW/K	400

NOTES:

1.Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under ªrecommended operating conditionsº is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

2.The input and output voltage ratings may be exceeded if the input and output current ratings are observed.

1998 Jun 10

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