INTEGRATED CIRCUITS
74LV374
Octal D-type flip-flop;
positive edge-trigger (3-State)
Product specification |
1997 Mar 20 |
Supersedes data of 1996 Feb
IC24 Data Handbook
m n r
Philips Semiconductors |
Product specification |
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Octal D-type flip-flop; positive edge-trigger (3-State) |
74LV374 |
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FEATURES
•Wide operating voltage: 1.0 to 5.5V
•Optimized for Low Voltage applications: 1.0 to 3.6V
•Accepts TTL input levels between VCC = 2.7V and VCC = 3.6V
•Typical VOLP (output ground bounce) 0.8V @ VCC = 3.3V, Tamb = 25°C
•Typical VOHV (output VOH undershoot) 2V @ VCC = 3.3V, Tamb = 25°C
•Common 3-State output enable input
•Output capability: bus driver
•ICC category: MSI
DESCRIPTION
The 74LV374 is a low-voltage Si-gate CMOS device and is pin and function compatible with 74HC/HCT374.
The 74LV374 is an octal D-type flip±flop featuring separate D-type inputs for each flip-flop and 3-state outputs for bus oriented
applications. A clock (CP) and an output enable (OE) input are common to all flip-flops.
The eight flip-flops will store the state of their individual D-inputs that meet the set-up and hold times requirements on the LOW-to-HIGH CP transition.
When OE is LOW, the contents of the eight flip-flops is available at the outputs. When OE is HIGH, the outputs go to the high impedance OFF-state. Operation of the OE input does not affect the state of the flip-flops.
QUICK REFERENCE DATA
GND = 0V; Tamb = 25°C; tr =tf 2.5 ns
SYMBOL |
PARAMETER |
CONDITIONS |
TYPICAL |
UNIT |
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tPHL/tPLH |
Propagation delay |
CL = 15pF |
14 |
ns |
CP to Qn |
VCC = 3.3V |
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fmax |
Maximum clock frequency |
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77 |
MHz |
CI |
Input capacitance |
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3.5 |
pF |
CPD |
Power dissipation capacitance per flip-flop |
Notes 1 and 2 |
25 |
pF |
NOTES:
1.CPD is used to determine the dynamic power dissipation (PD in mW) PD = CPD VCC2 x fi (CL VCC2 fo) where:
fi = input frequency in MHz; CL = output load capacity in pF;
fo = output frequency in MHz; VCC = supply voltage in V;(CL VCC2 fo) = sum of the outputs.
2.The condition is VI = GND to VCC
ORDERING INFORMATION
PACKAGES |
TEMPERATURE RANGE |
OUTSIDE NORTH AMERICA |
NORTH AMERICA |
PKG. DWG. # |
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20-Pin Plastic DIL |
±40°C to +125°C |
74LV374 N |
74LV374 N |
SOT146-1 |
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20-Pin Plastic SO |
±40°C to +125°C |
74LV374 D |
74LV374 D |
SOT163-1 |
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20-Pin Plastic SSOP Type II |
±40°C to +125°C |
74LV374 DB |
74LV374 DB |
SOT339-1 |
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PIN DESCRIPTION
PIN |
SYMBOL |
FUNCTION |
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NUMBER |
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1 |
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Output enable input (active-LOW) |
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OE |
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2, 5, 6, 9, 12, |
Q0 to Q7 |
3-State flip-flop outputs |
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15, 16, 19 |
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3, 4, 7, 8, 13, |
D0 to D7 |
Data inputs |
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14, 17, 18 |
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10 |
GND |
Ground (0V) |
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11 |
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CP |
Clock input (LOW-to-HIGH, edge- |
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triggered) |
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20 |
VCC |
Positive supply voltage |
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FUNCTION TABLE
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OPERATING |
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INPUTS |
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INTERNAL |
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OUTPUTS |
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MODES |
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CP |
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Dn |
FLIP-FLOPS |
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Q0 to Q7 |
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OE |
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Load and read |
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L |
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↑ |
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l |
L |
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L |
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register |
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L |
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↑ |
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h |
H |
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H |
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Load register and |
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H |
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↑ |
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l |
L |
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Z |
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disable outputs |
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H |
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↑ |
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h |
H |
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Z |
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H |
= HIGH voltage level |
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h |
= HIGH voltage level one set-up time prior to the |
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LOW-to-HIGH CP transition |
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L |
= LOW voltage level |
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l |
= LOW voltage level one set-up time prior to the |
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LOW-to-HIGH CP transition |
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Z |
= High impedance OFF-state |
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↑= LOW±to±HIGH clock transition
1997 Mar 20 |
2 |
Philips Semiconductors |
Product specification |
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Octal D-type flip-flop; positive edge-trigger (3-State) |
74LV374 |
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PIN CONFIGURATION
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VCC |
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OE |
1 |
20 |
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Q0 |
2 |
19 |
Q7 |
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D0 |
3 |
18 |
D7 |
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D1 |
4 |
17 |
D6 |
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Q1 |
5 |
16 |
Q6 |
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Q2 |
6 |
15 |
Q5 |
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D2 |
7 |
14 |
D5 |
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D3 |
8 |
13 |
D4 |
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Q3 |
9 |
12 |
Q4 |
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GND |
10 |
11 |
CP |
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SV00338 |
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LOGIC SYMBOL (IEEE/IEC)
11 |
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C1 |
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1 |
EN1 |
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3 |
2 |
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1D |
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4 |
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5 |
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7 |
6 |
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8 |
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13 |
12 |
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14 |
15 |
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17 |
16 |
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18 |
19 |
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SV00340 |
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LOGIC SYMBOL
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11 |
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3 |
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D0 |
CP |
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Q0 |
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2 |
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4 |
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D1 |
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Q1 |
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5 |
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7 |
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D2 |
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Q2 |
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6 |
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8 |
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D3 |
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Q3 |
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9 |
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13 |
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D4 |
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Q4 |
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12 |
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14 |
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D5 |
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Q5 |
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15 |
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17 |
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D6 |
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Q6 |
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16 |
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18 |
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D7 |
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Q7 |
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19 |
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OE |
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1 |
SV00339 |
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FUNCTIONAL DIAGRAM
3 |
D0 |
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Q0 |
2 |
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4 |
D1 |
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Q1 |
5 |
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7 |
D2 |
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Q2 |
6 |
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8 |
D3 |
FF1 |
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Q3 |
9 |
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3-STATE |
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to |
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13 |
D4 |
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OUTPUTS |
Q4 |
12 |
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FF8 |
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14 |
D5 |
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Q5 |
15 |
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17 |
D6 |
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Q6 |
16 |
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18 |
D7 |
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Q7 |
19 |
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11 |
CP |
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1 |
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OE |
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SV00341
LOGIC DIAGRAM
D0 |
D1 |
D2 |
D3 |
D4 |
D5 |
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D6 |
D7 |
D Q |
D Q |
D Q |
D Q |
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D Q |
D Q |
D Q |
D Q |
CP |
CP |
CP |
CP |
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CP |
CP |
CP |
CP |
FF1 |
FF2 |
FF3 |
FF4 |
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FF5 |
FF6 |
FF7 |
FF8 |
CP |
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OE |
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Q0 |
Q1 |
Q2 |
Q3 |
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Q4 |
Q5 |
Q6 |
Q7 |
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SV00342 |
1997 Mar 20 |
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3 |
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|
Philips Semiconductors |
Product specification |
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Octal D-type flip-flop; positive edge-trigger (3-State) |
74LV374 |
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ABSOLUTE MAXIMUM RATINGS1, 2
In accordance with the Absolute Maximum Rating System (IEC 134)
Voltages are referenced to GND (ground = 0V)
SYMBOL |
PARAMETER |
CONDITIONS |
RATING |
UNIT |
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VCC |
DC supply voltage |
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±0.5 to +7.0 |
V |
±IIK |
DC input diode current |
VI < ±0.5 or VI > VCC + 0.5V |
20 |
mA |
±IOK |
DC output diode current |
VO < ±0.5 or VO > VCC + 0.5V |
50 |
mA |
±IO |
DC output source or sink current |
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± standard outputs |
±0.5V < VO < VCC + 0.5V |
25 |
mA |
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± bus driver outputs |
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35 |
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±IGND, |
DC VCC or GND current for types with |
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±standard outputs |
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50 |
mA |
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±ICC |
±bus driver outputs |
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70 |
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Tstg |
Storage temperature range |
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±65 to +150 |
°C |
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Power dissipation per package |
for temperature range: ±40 to +125°C |
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PTOT |
±plastic DIL |
above +70°C derate linearly with 12mW/K |
750 |
mW |
±plastic mini-pack (SO) |
above +70°C derate linearly with 8 mW/K |
500 |
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±plastic shrink mini-pack (SSOP and TSSOP) |
above +60°C derate linearly with 5.5 mW/K |
400 |
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NOTES:
1.Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under ªrecommended operating conditionsº is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
2.The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
RECOMMENDED OPERATING CONDITIONS
SYMBOL |
PARAMETER |
CONDITIONS |
MIN |
TYP. |
MAX |
UNIT |
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VCC |
DC supply voltage |
See Note1 |
1.0 |
3.3 |
5.5 |
V |
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VI |
Input voltage |
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0 |
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VCC |
V |
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VO |
Output voltage |
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0 |
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VCC |
V |
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Tamb |
Operating ambient temperature range in free |
See DC and AC |
±40 |
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+85 |
°C |
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air |
characteristics per device |
±40 |
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+125 |
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Input rise and fall times except for |
VCC = 1.0V to 2.0V |
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± |
500 |
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tr, tf |
VCC = 2.0V to 2.7V |
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200 |
ns/V |
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Schmitt-trigger inputs |
VCC = 2.7V to 3.6V |
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100 |
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VCC = 3.6V to 5.5V |
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50 |
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NOTES:
1. The LV is guaranteed to function down to VCC = 1.0V (input levels GND or VCC); DC characteristics are guaranteed from VCC = 1.2V to VCC = 5.5V.
1997 Mar 20 |
4 |
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