Philips 74lv374 DATASHEETS
INTEGRATED CIRCUITS
74LV374
Octal D-type flip-flop;
positive edge-trigger (3-State)
Product specification
Supersedes data of 1996 Feb
IC24 Data Handbook
1997 Mar 20
Philips Semiconductors Product specification
Octal D-type flip-flop; positive edge-trigger (3-State)
FEATURES
•Wide operating voltage: 1.0 to 5.5V
•Optimized for Low Voltage applications: 1.0 to 3.6V
•Accepts TTL input levels between V
•Typical V
T
amb
•Typical V
T
amb
(output ground bounce) 0.8V @ VCC = 3.3V,
OLP
= 25°C
(output VOH undershoot) 2V @ VCC = 3.3V,
OHV
= 25°C
= 2.7V and VCC = 3.6V
CC
•Common 3-State output enable input
•Output capability: bus driver
•I
category: MSI
CC
QUICK REFERENCE DATA
GND = 0V; T
SYMBOL
t
PHL/tPLH
= 25°C; tr =tf 2.5 ns
amb
Propagation delay
CP to Q
PARAMETER CONDITIONS TYPICAL UNIT
n
DESCRIPTION
The 74LV374 is a low-voltage Si-gate CMOS device and is pin and
function compatible with 74HC/HCT374.
The 74LV374 is an octal D-type flip–flop featuring separate D-type
inputs for each flip-flop and 3-state outputs for bus oriented
applications. A clock (CP) and an output enable (OE
common to all flip-flops.
The eight flip-flops will store the state of their individual D-inputs that
meet the set-up and hold times requirements on the LOW-to-HIGH
CP transition.
When OE
the outputs. When OE
impedance OFF-state. Operation of the OE
state of the flip-flops.
CL = 15pF
VCC = 3.3V
is LOW, the contents of the eight flip-flops is available at
74L V374
) input are
is HIGH, the outputs go to the high
input does not affect the
14 ns
f
max
C
I
C
PD
NOTES:
is used to determine the dynamic power dissipation (PD in µW)
1. C
PD
= CPD V
P
D
= input frequency in MHz; CL = output load capacity in pF;
f
i
f
= output frequency in MHz; VCC = supply voltage in V;
o
V
(C
L
2. The condition is V
Maximum clock frequency 77 MHz
Input capacitance 3.5 pF
Power dissipation capacitance per flip-flop Notes 1 and 2 25 pF
2
x fi (CL V
CC
2
fo) = sum of the outputs.
CC
= GND to V
I
CC
2
fo) where:
CC
ORDERING INFORMATION
PACKAGES TEMPERATURE RANGE OUTSIDE NORTH AMERICA NORTH AMERICA PKG. DWG. #
20-Pin Plastic DIL –40°C to +125°C 74LV374 N 74LV374 N SOT146-1
20-Pin Plastic SO –40°C to +125°C 74LV374 D 74LV374 D SOT163-1
20-Pin Plastic SSOP Type II –40°C to +125°C 74LV374 DB 74LV374 DB SOT339-1
PIN DESCRIPTION
PIN
NUMBER
1 OE Output enable input (active-LOW)
2, 5, 6, 9, 12,
15, 16, 19
3, 4, 7, 8, 13,
14, 17, 18
10 GND Ground (0V)
11 CP
20 V
SYMBOL FUNCTION
Q0 to Q7 3-State flip-flop outputs
D0 to D7 Data inputs
Clock input (LOW-to-HIGH, edgetriggered)
CC
Positive supply voltage
FUNCTION TABLE
OPERATING
MODES
Load and read
register
Load register and
disable outputsHH↑↑lh
H = HIGH voltage level
h = HIGH voltage level one set-up time prior to the
LOW-to-HIGH CP transition
L = LOW voltage level
l = LOW voltage level one set-up time prior to the
LOW-to-HIGH CP transition
Z = High impedance OFF-state
↑ = LOW–to–HIGH clock transition
INPUTS
OE CP Dn
LL↑↑l
FLIP-FLOPS
h
INTERNAL
L
H
L
H
OUTPUTS
Q0 to Q7
L
H
Z
Z
1997 Mar 20
2
Philips Semiconductors Product specification
Octal D-type flip-flop; positive edge-trigger (3-State)
PIN CONFIGURATION
1
2
Q0
3
D0
4
D1
5
Q1
6
Q2
7
D2
8
D3
9
Q3
10 11
GND
LOGIC SYMBOL (IEEE/IEC)
11
1
3
4
7
8
13
14
17
18
C1
EN1
1D
20OE
19
18
17
16
15
14
13
12
SV00338
SV00340
V
Q7
D7
D6
Q6
Q5
D5
D4
Q4
CP
CC
2
5
6
9
12
15
16
19
LOGIC SYMBOL
FUNCTIONAL DIAGRAM
3
4
76
89
13 12
14 15
17 16
18 19
11
1
D
D
D
D
D
D
D
D
CP
OE
74LV374
11
3
4
7
8
13
14
17
18
0
1
2
3
FF1
to
4
FF8
5
6
7
CP
D0
D1
D2
D3
D4
D5
D6
D7
OE
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
1
OUTPUTS
SV00339
3-STATE
2
5
6
9
12
15
16
19
2
Q
0
5
Q
1
Q
2
Q
3
Q
4
Q
5
Q
6
Q
7
LOGIC DIAGRAM
D0
CP
OE
1997 Mar 20
SV00341
D1 D2 D3 D4 D5 D6 D7
D
Q
CP
FF1 FF2 FF3 FF4 FF5 FF6 FF7 FF8
Q0
D Q
CP
D Q
CP
Q1 Q2 Q3 Q4 Q5 Q6 Q7
D Q
CP
D Q
CP
D Q
CP
D Q
CP
3
D Q
CP
SV00342
Philips Semiconductors Product specification
Octal D-type flip-flop; positive edge-trigger (3-State)
ABSOLUTE MAXIMUM RATINGS
1, 2
74LV374
In accordance with the Absolute Maximum Rating System (IEC 134)
Voltages are referenced to GND (ground = 0V)
SYMBOL
V
CC
±I
IK
±I
OK
DC supply voltage –0.5 to +7.0 V
DC input diode current VI < –0.5 or VI > VCC + 0.5V 20 mA
DC output diode current VO < –0.5 or VO > VCC + 0.5V 50 mA
PARAMETER CONDITIONS RATING UNIT
DC output source or sink current
±I
– standard outputs
O
– bus driver outputs
–0.5V < VO < VCC + 0.5V
25
35
mA
DC VCC or GND current for types with
±I
,
±I
P
GND
CC
T
stg
TOT
–standard outputs
–bus driver outputs
Storage temperature range –65 to +150 °C
Power dissipation per package
–plastic DIL
–plastic mini-pack (SO)
–plastic shrink mini-pack (SSOP and TSSOP)
for temperature range: –40 to +125°C
above +70°C derate linearly with 12mW/K
above +70°C derate linearly with 8 mW/K
above +60°C derate linearly with 5.5 mW/K
50
70
750
500
400
mA
mW
NOTES:
1. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the
device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to
absolute-maximum-rated conditions for extended periods may affect device reliability .
2. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
RECOMMENDED OPERATING CONDITIONS
SYMBOL PARAMETER CONDITIONS MIN TYP. MAX UNIT
V
CC
V
V
T
amb
tr, t
NOTES:
1. The LV is guaranteed to function down to V
DC supply voltage See Note1 1.0 3.3 5.5 V
Input voltage 0 – V
I
Output voltage 0 – V
O
Operating ambient temperature range in free
air
Input rise and fall times except for
f
Schmitt-trigger inputs
= 1.0V (input levels GND or VCC); DC characteristics are guaranteed from VCC = 1.2V to VCC = 5.5V.
CC
See DC and AC
characteristics per device
VCC = 1.0V to 2.0V
VCC = 2.0V to 2.7V
VCC = 2.7V to 3.6V
VCC = 3.6V to 5.5V
–40
–40
–
–
–
–
–
–
–
CC
CC
+85
+125
500
200
100
50
V
V
°C
ns/V
1997 Mar 20
4
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