INTEGRATED CIRCUITS
74LV373
Octal D-type transparent latch (3-State)
Product specification |
1998 Jun 10 |
Supersedes data of 1997 March 04
IC24 Data Handbook
m n r
Philips Semiconductors |
Product specification |
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Octal D-type transparent latch (3-State) |
74LV373 |
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FEATURES
•Wide operating voltage: 1.0 to 5.5V
•Optimized for Low Voltage applications: 1.0V to 3.6V
•Accepts TTL input levels between VCC = 2.7V and VCC = 3.6V
•Typical VOLP (output ground bounce) < 0.8V at VCC = 3.3V, Tamb = 25°C
•Typical VOHV (output VOH undershoot) > 2V at VCC = 3.3V, Tamb = 25°C
•Common 3-State output enable input
•Output capability: bus driver
•ICC category: MSI
QUICK REFERENCE DATA
GND = 0V; Tamb = 25°C; tr = tf 2.5 ns
DESCRIPTION
The 74LV373 is a low-voltage Si-gate CMOS device that is pin and function compatible with 74HC/HCT373.
The 74LV373 is an octal D-type transparent latch featuring separate
D-type inputs for each latch and 3-State outputs for bus oriented
applications. A latch enable (LE) input and an output enable (OE) input are common to all internal latches.
The `373' consists of eight D-type transparent latches with 3-State true outputs. When LE is HIGH, data at the Dn inputs enters the latches. In this condition the latches are transparent, i.e., a latch output will change each time its corresponding D-input changes.
When LE is LOW the latches store the information that was present at the D-inputs a set-up time preceding the HIGH-to-LOW transition of LE. When OE is LOW, the contents of the eight latches are
available at the outputs. When OE is HIGH, the outputs go to the high impedance OFF-state. Operation of the OE input does not affect the state of the latches.
The `373' is functionally identical to the `573', but the `573' has a different pin arrangement.
SYMBOL |
PARAMETER |
CONDITIONS |
TYPICAL |
UNIT |
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Propagation delay |
CL = 15pF |
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tPHL/tPLH |
Dn to Qn |
VCC = 3.3V |
10 |
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LE to Qn |
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12 |
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CI |
Input capacitance |
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3.5 |
pF |
CPD |
Power dissipation capacitance per latch |
Notes 1, 2 |
22 |
pF |
NOTES:
1.CPD is used to determine the dynamic power dissipation (PD in μW)
PD = CPD VCC2 x fi (CL VCC2 fo) where:
fi = input frequency in MHz; CL = output load capacity in pF;
fo = output frequency in MHz; VCC = supply voltage in V;
(CL VCC2 fo) = sum of the outputs.
2.The condition is VI = GND to VCC.
ORDERING AND PACKAGE INFORMATION
PACKAGES |
TEMPERATURE RANGE |
OUTSIDE NORTH AMERICA |
NORTH AMERICA |
PKG. DWG. # |
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20-Pin Plastic DIL |
±40°C to +125°C |
74LV373 N |
74LV373 N |
SOT146-1 |
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20-Pin Plastic SO |
±40°C to +125°C |
74LV373 D |
74LV373 D |
SOT163-1 |
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20-Pin Plastic SSOP Type II |
±40°C to +125°C |
74LV373 DB |
74LV373 DB |
SOT339-1 |
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20-Pin Plastic TSSOP Type I |
±40°C to +125°C |
74LV373 PW |
74LV373PW DH |
SOT360-1 |
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PIN DESCRIPTION
PIN NUMBER |
SYMBOL |
FUNCTION |
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1 |
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Output enabled input (active LOW) |
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OE |
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2, 5, 6, 9, 12, |
Q0±Q7 |
3-State latch outputs |
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15, 16, 19 |
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3, 4, 7, 8, 13, |
D0±D7 |
Data inputs |
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14, 17, 18 |
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10 |
GND |
Ground (0V) |
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11 |
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LE |
Latch enable input (active HIGH) |
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20 |
VCC |
Positive supply voltage |
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1998 Jun 10 |
2 |
853±1934 19545 |
Philips Semiconductors |
Product specification |
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Octal D-type transparent latch (3-State) |
74LV373 |
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PIN CONFIGURATION |
LOGIC SYMBOL |
OE |
1 |
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20 |
VCC |
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11 |
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Q0 |
2 |
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19 |
Q7 |
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LE |
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D0 |
3 |
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18 |
D7 |
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3 |
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D0 |
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Q0 |
2 |
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4 |
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D1 |
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5 |
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D1 |
4 |
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17 |
D6 |
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Q1 |
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7 |
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D2 |
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Q2 |
6 |
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Q1 |
5 |
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16 |
Q6 |
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8 |
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D3 |
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Q3 |
9 |
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Q2 |
6 |
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15 |
Q5 |
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13 |
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D4 |
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Q4 |
12 |
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D2 |
7 |
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14 |
D5 |
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14 |
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D5 |
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Q5 |
15 |
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D3 |
8 |
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13 D4 |
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17 |
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D6 |
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Q6 |
16 |
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Q3 |
9 |
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12 Q4 |
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18 |
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D7 |
OE |
Q7 |
19 |
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GND |
10 |
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11 |
LE |
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SV00657 |
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1 |
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SV00658 |
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LOGIC SYMBOL (IEEE/IEC) |
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FUNCTIONAL DIAGRAM |
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11 |
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C1 |
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3 |
D0 |
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Q0 |
2 |
1 |
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EN1 |
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4 |
D1 |
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Q1 |
5 |
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3 |
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2 |
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7 |
D2 |
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Q2 |
6 |
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1D |
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8 |
D3 |
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Q3 |
9 |
4 |
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5 |
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13 |
D4 |
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LATCH |
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3±STATE |
Q4 |
12 |
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1 to 8 |
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OUTPUTS |
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7 |
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6 |
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14 |
D5 |
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15 |
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Q5 |
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8 |
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9 |
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17 |
D6 |
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Q6 |
16 |
13 |
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12 |
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18 |
D7 |
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Q7 |
19 |
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14 |
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15 |
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17 |
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16 |
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11 |
LE |
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18 |
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19 |
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1 |
OE |
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SV00659 |
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SV00660 |
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LOGIC DIAGRAM |
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D0 |
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D1 |
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D2 |
D3 |
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D4 |
D5 |
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D6 |
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D7 |
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D Q |
D Q |
D Q |
D Q |
D Q |
D Q |
D Q |
D Q |
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LATCH |
LATCH |
LATCH |
LATCH |
LATCH |
LATCH |
LATCH |
LATCH |
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1 |
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2 |
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3 |
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4 |
5 |
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6 |
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7 |
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8 |
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LE |
LE |
LE |
LE |
LE |
LE |
LE LE |
LE |
LE |
LE |
LE |
LE |
LE |
LE |
LE |
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LE |
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OE |
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Q0 |
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Q1 |
Q2 |
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Q3 |
Q4 |
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Q5 |
Q6 |
Q7 |
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SV00661 |
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1998 Jun 10 |
3 |
Philips Semiconductors |
Product specification |
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Octal D-type transparent latch (3-State) |
74LV373 |
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FUNCTION TABLE
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OPERATING MODES |
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INPUTS |
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INTERNAL |
OUTPUTS |
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LATCHES |
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OE |
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LE |
Dn |
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Q0 to Q7 |
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Enable and read register |
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L |
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H |
L |
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L |
L |
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(transparent mode) |
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L |
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H |
H |
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H |
H |
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Latch and read register |
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L |
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L |
I |
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L |
L |
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L |
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L |
h |
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H |
H |
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Latch register and disable outputs |
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H |
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L |
I |
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L |
Z |
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H |
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L |
h |
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H |
Z |
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H = HIGH voltage level |
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h = HIGH voltage level one set-up time prior to the HIGH-to-LOW LE transition |
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L |
= LOW voltage level |
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I |
= LOW voltage level one set-up time prior to the HIGH-to-LOW LE transition |
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X |
= Don't care |
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Z = High impedance OFF-state
RECOMMENDED OPERATING CONDITIONS
SYMBOL |
PARAMETER |
CONDITIONS |
MIN |
TYP. |
MAX |
UNIT |
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VCC |
DC supply voltage |
See Note1 |
1.0 |
3.3 |
5.5 |
V |
VI |
Input voltage |
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0 |
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VCC |
V |
VO |
Output voltage |
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0 |
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VCC |
V |
Tamb |
Operating ambient temperature range in free |
See DC and AC |
±40 |
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+85 |
°C |
air |
characteristics |
±40 |
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+125 |
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VCC = 1.0V to 2.0V |
± |
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500 |
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tr, tf |
Input rise and fall times |
VCC = 2.0V to 2.7V |
± |
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200 |
ns/V |
VCC = 2.7V to 3.6V |
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100 |
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VCC = 3.6V to 5.5V |
± |
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50 |
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NOTE:
1. The LV is guaranteed to function down to VCC = 1.0V (input levels GND or VCC); DC characteristics are guaranteed from VCC = 1.2V to VCC = 5.5V.
ABSOLUTE MAXIMUM RATINGS1, 2
In accordance with the Absolute Maximum Rating System (IEC 134).
Voltages are referenced to GND (ground = 0V).
SYMBOL |
PARAMETER |
CONDITIONS |
RATING |
UNIT |
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VCC |
DC supply voltage |
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±0.5 to +7.0 |
V |
±IIK |
DC input diode current |
VI < ±0.5 or VI > VCC + 0.5V |
20 |
mA |
±IOK |
DC output diode current |
VO < ±0.5 or VO > VCC + 0.5V |
50 |
mA |
±IO |
DC output source or sink current |
±0.5V < VO < VCC + 0.5V |
35 |
mA |
± bus driver outputs |
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±IGND, |
DC VCC or GND current for types with |
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70 |
mA |
±bus driver outputs |
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±ICC |
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Tstg |
Storage temperature range |
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±65 to +150 |
°C |
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Power dissipation per package |
for temperature range: ±40 to +125°C |
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Ptot |
±plastic DIL |
above +70°C derate linearly with 12mW/K |
750 |
mW |
±plastic mini-pack (SO) |
above +70°C derate linearly with 8 mW/K |
500 |
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±plastic shrink mini-pack (SSOP and TSSOP) |
above +60°C derate linearly with 5.5 mW/K |
400 |
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NOTES:
1.Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under ªrecommended operating conditionsº is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
2.The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
1998 Jun 10 |
4 |
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