Philips 74LV373PW, 74LV373N, 74LV373D Datasheet

74LV373
Octal D-type transparent latch (3-State)
Product specification Supersedes data of 1997 March 04 IC24 Data Handbook
 
1998 Jun 10
Philips Semiconductors Product specification
74L V373Octal D-type transparent latch (3-State)
FEA TURES
Wide operating voltage: 1.0 to 5.5V
Optimized for Low Voltage applications: 1.0V to 3.6V
Accepts TTL input levels between V
Typical V
T
amb
Typical V
T
amb
(output ground bounce) < 0.8V at V
OLP
= 25°C
(output VOH undershoot) > 2V at V
OHV
= 25°C
= 2.7V and V
CC
CC
CC
Common 3-State output enable input
Output capability: bus driver
I
category: MSI
CC
QUICK REFERENCE DATA
GND = 0V; T
SYMBOL
t
PHL/tPLH
C
I
C
PD
NOTES:
is used to determine the dynamic power dissipation (PD in µW)
1. C
PD
P
= CPD V
D
= input frequency in MHz; CL = output load capacity in pF;
f
i
f
= output frequency in MHz; VCC = supply voltage in V;
o
(C
2. The condition is V
= 25°C; tr = tf 2.5 ns
amb
CC
2
V
L
fo) = sum of the outputs.
CC
PARAMETER CONDITIONS TYPICAL UNIT
Propagation delay D
to Q
n
n
LE to Q
n
Input capacitance 3.5 pF Power dissipation capacitance per latch Notes 1, 2 22 pF
2
x fi  (CL V
= GND to V
I
CC.
2
fo) where:
CC
= 3.6V
CC
= 3.3V ,
= 3.3V ,
DESCRIPTION
The 74LV373 is a low-voltage Si-gate CMOS device that is pin and function compatible with 74HC/HCT373.
The 74LV373 is an octal D-type transparent latch featuring separate D-type inputs for each latch and 3-State outputs for bus oriented applications. A latch enable (LE) input and an output enable (OE input are common to all internal latches.
The ‘373’ consists of eight D-type transparent latches with 3-State true outputs. When LE is HIGH, data at the Dn inputs enters the latches. In this condition the latches are transparent, i.e., a latch output will change each time its corresponding D-input changes.
When LE is LOW the latches store the information that was present at the D-inputs a set-up time preceding the HIGH-to-LOW transition of LE. When OE available at the outputs. When OE high impedance OFF-state. Operation of the OE affect the state of the latches.
The ‘373’ is functionally identical to the ‘573’, but the ‘573’ has a different pin arrangement.
CL = 15pF VCC = 3.3V 10
is LOW, the contents of the eight latches are
is HIGH, the outputs go to the
input does not
12
)
ns
ORDERING AND PACKAGE INFORMA TION
PACKAGES TEMPERATURE RANGE OUTSIDE NORTH AMERICA NORTH AMERICA PKG. DWG. #
20-Pin Plastic DIL –40°C to +125°C 74LV373 N 74LV373 N SOT146-1 20-Pin Plastic SO –40°C to +125°C 74LV373 D 74LV373 D SOT163-1 20-Pin Plastic SSOP Type II –40°C to +125°C 74LV373 DB 74LV373 DB SOT339-1 20-Pin Plastic TSSOP Type I –40°C to +125°C 74L V373 PW 74LV373PW DH SOT360-1
PIN DESCRIPTION
PIN NUMBER SYMBOL FUNCTION
1 OE Output enabled input (active LOW)
2, 5, 6, 9, 12,
15, 16, 19
3, 4, 7, 8, 13,
14, 17, 18
10 GND Ground (0V) 11 LE Latch enable input (active HIGH) 20 V
1998 Jun 10 853–1934 19545
Q0–Q73-State latch outputs
D0–D
CC
Data inputs
7
Positive supply voltage
2
Philips Semiconductors Product specification
74LV373Octal D-type transparent latch (3-State)
PIN CONFIGURATION
1
OE
2
Q
0
3
D
0
4
D
1
5
Q
1
6
Q
2
7
D
2
8
D
3
9
Q
3
10
GND
LOGIC SYMBOL (IEEE/IEC)
11
1
3
4
7
8
13
14
17
18
C1 EN1
1D
20
V
19
Q
18
D
17
D
16
Q
15
Q
14
D
13
D Q
12
11
LE
SV00657
LOGIC SYMBOL
CC
7
7
6
6
5
5
4
4
3
D
4
D
7
D
8
D
13
D
14
D
17
D
18
D
11
LE
OE
Q
0
Q
1
Q
2
Q
3
Q
4
Q
5
Q
6
Q
7
0
1
2
3
4
5
6
7
1
2 5 6
9 12 15 16 19
SV00658
FUNCTIONAL DIAGRAM
3
D
0
4
D
1
7
D
2
5
6
9
12
2
8
D
3
13
D
4
D
14
5
D
17
6
D
18
7
LATCH 1 to 8
3–STATE OUTPUTS
15
LE
16
19
11
1
OE
2
Q
0
5
Q
1
6
Q
2
9
Q
3
12
Q
4
15
Q
5
16
Q
6
19
Q
7
LOGIC DIAGRAM
D
0
LE
OE
1998 Jun 10
D LATCH
1
LE
LE
SV00659
D
1
Q
D LATCH
2 LE
Q0
D
2
Q
LE
D LATCH
3 LE
Q1
D
3
Q
LE
D LATCH
4 LE
Q2
D
4
Q
LE
D LATCH
5 LE
Q3
D
5
Q
LE
D LATCH
6 LE
Q4
D
6
Q
LE
D LATCH
7 LE
Q5
D
7
Q
LE
Q6
D LATCH
8 LE
SV00660
Q
LE
Q7
SV00661
3
Philips Semiconductors Product specification
OPERATING MODES
P
mW
74LV373Octal D-type transparent latch (3-State)
FUNCTION TABLE
Enable and read register (transparent mode)
Latch and read register
Latch register and disable outputs
INPUTS
OE LE Dn
L L
L L
H H
H H
H
L L
L L
L
I
h
I
h
INTERNAL
LATCHES
L
H
L
H
L
H
H = HIGH voltage level h = HIGH voltage level one set-up time prior to the HIGH-to-LOW LE transition L = LOW voltage level I = LOW voltage level one set-up time prior to the HIGH-to-LOW LE transition X = Don’t care Z = High impedance OFF-state
RECOMMENDED OPERATING CONDITIONS
SYMBOL PARAMETER CONDITIONS MIN TYP. MAX UNIT
V
CC
V
V
T
amb
tr, t
NOTE:
1. The LV is guaranteed to function down to V
DC supply voltage See Note1 1.0 3.3 5.5 V Input voltage 0 V
I
Output voltage 0 V
O
Operating ambient temperature range in free air
Input rise and fall times
f
= 1.0V (input levels GND or VCC); DC characteristics are guaranteed from VCC = 1.2V to VCC = 5.5V.
CC
See DC and AC characteristics
VCC = 1.0V to 2.0V VCC = 2.0V to 2.7V VCC = 2.7V to 3.6V V
= 3.6V to 5.5V
CC
–40 –40
– – – –
– – – –
OUTPUTS
Q0 to Q
L
H
L
H
Z Z
CC CC
+85
+125
500 200 100
50
7
V V
°C
ns/V
ABSOLUTE MAXIMUM RATINGS
1, 2
In accordance with the Absolute Maximum Rating System (IEC 134). Voltages are referenced to GND (ground = 0V).
SYMBOL
V
CC
±I
IK
±I
OK
±I
O
±I
GND
±I
CC
T
stg
DC supply voltage –0.5 to +7.0 V DC input diode current VI < –0.5 or VI > VCC + 0.5V 20 mA DC output diode current VO < –0.5 or VO > VCC + 0.5V 50 mA DC output source or sink current
– bus driver outputs DC VCC or GND current for types with
,
–bus driver outputs Storage temperature range –65 to +150 °C
PARAMETER CONDITIONS RATING UNIT
–0.5V < VO < VCC + 0.5V 35 mA
70 mA
Power dissipation per package for temperature range: –40 to +125°C –plastic DIL above +70°C derate linearly with 12mW/K 750
tot
–plastic mini-pack (SO) above +70°C derate linearly with 8 mW/K 500 –plastic shrink mini-pack (SSOP and TSSOP) above +60°C derate linearly with 5.5 mW/K 400
NOTES:
1. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability .
2. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
1998 Jun 10
4
Loading...
+ 8 hidden pages