INTEGRATED CIRCUITS
74LV273
Octal D-type flip-flop with reset; positive-edge trigger
Product specification |
1998 May 29 |
Supersedes data of 1997 Apr 07
IC24 Data Handbook
m n r
Philips Semiconductors |
Product specification |
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Octal D-type flip-flop with reset; positive edge-trigger |
74LV273 |
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FEATURES
•Wide operating voltage: 1.0 to 5.5V
•Optimized for Low Voltage applications: 1.0 to 3.6V
•Accepts TTL input levels between VCC = 2.7V and VCC = 3.6V
•Typical VOLP (output ground bounce) 0.8V @ VCC = 3.3V, Tamb = 25°C
•Typical VOHV (output VOH undershoot) 2V @ VCC = 3.3V, Tamb = 25°C
•Ideal buffer for MOS microprocessor or memory
•Common clock and master reset
•Output capability: standard
•ICC category: MSI
DESCRIPTION
The 74LV273 is a low-voltage Si-gate CMOS device and is pin and function compatible with the 74HC/HCT273.
The 74LV273 has eight edge-triggered , D-type flip-flops with individual D inputs and Q outputs. The common clock (CP) and
master reset (MR) inputs load and reset (clear) all flip-flops simultaneously. The state of each D input, one set-up time before the LOW-to-HIGH clock transition, is transferred to the corresponding output (Qn) of the flip-flop.
All outputs will be forced LOW independently of clock or data inputs by a LOW voltage level on the MR input.
The device is useful for applications where the true output only is required and the clock and master reset are common to all storage elements.
QUICK REFERENCE DATA
GND = 0V; Tamb = 25°C; tr =tf 2.5 ns
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SYMBOL |
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PARAMETER |
CONDITIONS |
TYPICAL |
UNIT |
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Propagation delay |
CL = 15pF |
12 |
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t |
/t |
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CP to Q |
ns |
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13 |
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PHL |
PLH |
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n; |
VCC = 3.3V |
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MR |
to Qn |
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fmax |
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Maximum clock frequency |
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110 |
MHz |
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CI |
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Input capacitance |
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3.5 |
pF |
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CPD |
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Power dissipation capacitance per flip-flop |
Notes 1 and 2 |
20 |
pF |
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NOTES:
1.CPD is used to determine the dynamic power dissipation (PD in μW) PD = CPD VCC2 x fi (CL VCC2 fo) where:
fi = input frequency in MHz; CL = output load capacitance in pF;
fo = output frequency in MHz; VCC = supply voltage in V;(CL VCC2 fo) = sum of the outputs.
2.The condition is VI = GND to VCC
ORDERING INFORMATION
PACKAGES |
TEMPERATURE RANGE |
OUTSIDE NORTH AMERICA |
NORTH AMERICA |
PKG. DWG. # |
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20-Pin Plastic DIL |
±40°C to +125°C |
74LV273 N |
74LV273 N |
SOT146-1 |
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20-Pin Plastic SO |
±40°C to +125°C |
74LV273 D |
74LV273 D |
SOT163-1 |
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20-Pin Plastic SSOP Type II |
±40°C to +125°C |
74LV273 DB |
74LV273 DB |
SOT339-1 |
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20-Pin Plastic TSSOP |
±40°C to +125°C |
74LV273 PW |
74LV273PW DH |
SOT360-1 |
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1998 May 29 |
2 |
853±1965 19466 |
Philips Semiconductors |
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Product specification |
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Octal D-type flip-flop with reset; positive edge-trigger |
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74LV273 |
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PIN CONFIGURATION |
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LOGIC SYMBOL |
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1 |
20 |
VCC |
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CP |
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MR |
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3 |
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D0 |
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Q0 |
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2 |
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Q0 |
2 |
19 |
Q7 |
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4 |
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D1 |
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Q1 |
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5 |
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D0 |
3 |
18 |
D7 |
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7 |
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D2 |
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Q2 |
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6 |
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D1 |
4 |
17 |
D6 |
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Q1 |
5 |
16 |
Q6 |
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8 |
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D3 |
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Q3 |
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Q2 |
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15 |
Q5 |
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13 |
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D4 |
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Q4 |
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12 |
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D2 |
7 |
14 |
D5 |
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14 |
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D5 |
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Q5 |
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15 |
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D3 |
8 |
13 |
D4 |
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17 |
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D6 |
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Q6 |
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16 |
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Q3 |
9 |
12 |
Q4 |
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18 |
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D7 |
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Q7 |
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19 |
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GND |
10 |
11 |
CP |
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MR |
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1 |
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SV00366 |
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SV00367 |
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PIN DESCRIPTION
PIN |
SYMBOL |
FUNCTION |
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NUMBER |
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1 |
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Master reset input (active-LOW) |
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MR |
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2, 5, 6, 9, 12, |
Q0 to Q7 |
Flip-flop outputs |
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15, 16, 19 |
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3, 4, 7, 8, 13, |
D0 to D7 |
Data inputs |
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14, 17, 18 |
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10 |
GND |
Ground (0V) |
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11 |
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CP |
Clock input (LOW-to-HIGH, edge- |
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triggered) |
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20 |
VCC |
Positive supply voltage |
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LOGIC SYMBOL (IEEE/IEC)
11 |
C1 |
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1 |
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R |
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3 |
1D |
2 |
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4 |
5 |
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7 |
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6 |
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8 |
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9 |
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13 |
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12 |
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14 |
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15 |
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17 |
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16 |
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18 |
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19 |
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SV00368
1998 May 29 |
3 |
Philips Semiconductors |
Product specification |
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Octal D-type flip-flop with reset; positive edge-trigger |
74LV273 |
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FUNCTIONAL DIAGRAM
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3 |
D0 |
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Q0 |
2 |
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4 |
D1 |
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Q1 |
5 |
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7 |
D2 |
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Q2 |
6 |
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8 |
D3 |
FF0 |
Q3 |
9 |
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13 |
D4 |
to |
Q4 |
12 |
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FF7 |
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14 |
D5 |
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Q5 |
15 |
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17 |
D6 |
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Q6 |
16 |
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18 |
D7 |
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Q7 |
19 |
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1 |
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MR |
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11 |
CP |
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SV00369 |
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FUNCTION TABLE
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OPERATING MODES |
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INPUTS |
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OUTPUTS |
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MR |
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CP |
Dn |
Q0 to Q7 |
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Reset (clear) |
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L |
X |
X |
L |
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Load (`1') |
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H |
↑ |
h |
H |
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Load (`0') |
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H |
↑ |
l |
L |
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H |
= |
HIGH voltage level |
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h |
= HIGH voltage level one set-up time prior to the |
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LOW-to-HIGH CP transition |
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L |
= |
LOW voltage level |
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l= LOW voltage level one set-up time prior to the LOW-to-HIGH CP transition
↑ |
= |
LOW±to±HIGH clock transition |
X |
= |
Don't care |
RECOMMENDED OPERATING CONDITIONS
SYMBOL |
PARAMETER |
CONDITIONS |
MIN |
TYP. |
MAX |
UNIT |
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VCC |
DC supply voltage |
See Note1 |
1.0 |
3.3 |
5.5 |
V |
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VI |
Input voltage |
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0 |
± |
VCC |
V |
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VO |
Output voltage |
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0 |
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VCC |
V |
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Tamb |
Operating ambient temperature range in free |
See DC and AC |
±40 |
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+85 |
°C |
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air |
characteristics |
±40 |
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+125 |
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VCC = 1.0V to 2.0V |
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500 |
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tr, tf |
Input rise and fall times |
VCC = 2.0V to 2.7V |
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200 |
ns/V |
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VCC = 2.7V to 3.6V |
± |
100 |
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VCC = 3.6V to 5.5V |
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50 |
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NOTES:
1. The LV is guaranteed to function down to VCC = 1.0V (input levels GND or VCC); DC characteristics are guaranteed from VCC = 1.2V to VCC = 5.5V.
1998 May 29 |
4 |
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