INTEGRATED CIRCUITS
74LV259
8-bit addressable latch
Product specification |
1998 May 20 |
Supersedes data of 1997 Jun 06
IC24 Data Handbook
m n r
Philips Semiconductors |
Product specification |
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8-bit addressable latch |
74LV259 |
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FEATURES
•Optimized for low voltage applications: 1.0 to 3.6 V
•Accepts TTL input levels between VCC = 2.7 V and VCC = 3.6 V
•Typical VOLP (output ground bounce) < 0.8 V at VCC = 3.3 V, Tamb = 25°C
•Typical VOHV (output VOH undershoot) > 2 V at VCC = 3.3 V, Tamb = 25°C
•Combines demultiplexer and 8-bit latch
•Serial-to-parallel capability
•Output from each storage bit available
•Random (addressable) data entry
•Easily expandable
•Common reset input
•Useful as a 3-to-8 active HIGH decoder
•Output capability: standard
•ICC category: MSI
DESCRIPTION
The 74LV259 is a low-voltage CMOS device and is pin and function compatible with 74HC/HCT259.
The 74LV259 is a high-speed 8-bit addressable latch designed for general purpose storage applications in digital systems. The
74LV259 is a multifunction device capable of storing single-line data in eight addressable latches, and also 3-to-8 decoder and demultiplexer, with active HIGH outputs (Q0 to Q7), functions are available. The 74LV259 also incorporate an active LOW common reset (MR) for resetting all latches, as well as an active LOW enable input (LE). The 74LV259 has four modes of operation as shown in the mode select table. In the addressable latch mode, data on the data line (D) is written into the addressed latch. The addressed latch will follow the data input with all non-addressed latches remaining in their previous states. In the memory mode, all latches remain in their previous states and are unaffected by the data or address inputs.
In the 3-to-8 decoding or demultiplexing mode, the addressed output follows the state of the D input with all other outputs in the LOW state. In the reset mode all outputs are LOW and unaffected by the address (A0 to A2) and date (D) input. When operating the 74LV259 as an addressable latch, changing more than one bit of address could impose a transient-wrong address. Therefore, this should only be done while in the memory mode. The mode select table summarizes the operations of the 74LV259.
QUICK REFERENCE DATA
GND = 0 V; Tamb = 25°C; tr = tf ≤ 2.5 ns
SYMBOL |
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PARAMETER |
CONDITIONS |
TYPICAL |
UNIT |
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Propagation delay |
CL = 15 pF; |
17 |
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tPHL/tPLH |
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D, An to Qn |
VCC = 3.3 V |
ns |
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LE |
to Qn |
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16 |
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MR |
to Qn |
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14 |
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CI |
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Input capacitance |
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3.5 |
pF |
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CPD |
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Power dissipation capacitance per latch |
VI = GND to VCC1 |
19 |
pF |
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NOTE:
1.CPD is used to determine the dynamic power dissipation (PD in mW) PD = CPD × VCC2 × fi (CL × VCC2 × fo) where:
fi = input frequency in MHz; CL = output load capacity in pF;
fo = output frequency in MHz; VCC = supply voltage in V;
(CL × VCC2 × fo) = sum of the outputs.
ORDERING INFORMATION
PACKAGES |
TEMPERATURE RANGE |
OUTSIDE NORTH AMERICA |
NORTH AMERICA |
PKG. DWG. # |
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16-Pin Plastic DIL |
±40°C to +125°C |
74LV259 N |
74LV259 N |
SOT38-4 |
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16-Pin Plastic SO |
±40°C to +125°C |
74LV259 D |
74LV259 D |
SOT109-1 |
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16-Pin Plastic SSOP Type II |
±40°C to +125°C |
74LV259 DB |
74LV259 DB |
SOT338-1 |
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16-Pin Plastic TSSOP Type I |
±40°C to +125°C |
74LV259 PW |
74LV259PW DH |
SOT403-1 |
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1998 May 20 |
2 |
853-1988 19420 |
Philips Semiconductors |
Product specification |
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8-bit addressable latch |
74LV259 |
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PIN CONFIGURATION
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A0 |
1 |
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16 |
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VCC |
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A1 |
2 |
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15 |
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MR |
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A2 |
3 |
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14 |
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LE |
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Q0 |
4 |
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13 |
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D |
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Q1 |
5 |
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12 |
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Q7 |
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Q2 |
6 |
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11 |
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Q6 |
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Q3 |
7 |
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10 |
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Q5 |
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GND |
8 |
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9 |
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Q4 |
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SV01602 |
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LOGIC SYMBOL
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14 |
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LE |
Q0 |
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4 |
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13 |
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D |
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Q1 |
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5 |
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Q2 |
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6 |
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1 |
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Q3 |
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7 |
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A0 |
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Q4 |
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2 |
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A1 |
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Q5 |
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10 |
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3 |
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A2 |
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Q6 |
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11 |
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MR |
Q7 |
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12 |
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SV01601 |
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15 |
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FUNCTIONAL DIAGRAM |
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Q0 |
4 |
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1 |
A0 |
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Q1 |
5 |
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2 |
A1 |
1-of±8 |
Q2 |
6 |
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DECODER |
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3 |
A2 |
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Q |
3 |
7 |
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8 LATCHES |
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Q4 |
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14 |
LE |
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Q5 |
10 |
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15 |
MR |
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Q6 |
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13 |
D |
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Q7 |
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PIN DESCRIPTION
PIN |
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SYMBOL |
FUNCTION |
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NUMBER |
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1, 2, 3 |
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A0 to A2 |
Address inputs |
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4, 5, 6, 7, 9, |
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Q0 to Q7 |
Latch outputs |
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10, 11, 12 |
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8 |
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GND |
Ground (0 V) |
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13 |
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D |
Data input |
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14 |
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Latch enable input (active LOW) |
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LE |
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15 |
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Conditional reset input (active LOW) |
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MR |
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16 |
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VCC |
Positive supply voltage |
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LOGIC SYMBOL (IEEE/IEC) |
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15 |
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G8 |
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13 |
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Z9 |
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DX |
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9, 10D |
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0 |
1 |
C10 |
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4 |
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8R |
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1 |
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0 |
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5 |
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2 |
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1 |
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0 |
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3 |
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G 7 |
2 |
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6 |
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14 |
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2 |
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3 |
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7 |
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4 |
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9 |
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5 |
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10 |
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6 |
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11 |
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7 |
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12 |
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SV01603 |
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MODE SELECT TABLE |
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LE |
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MR |
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MODE |
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L |
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H |
Addressable latch |
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H |
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H |
Memory |
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L |
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L |
Active HIGH 8-channel demultiplexer |
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H |
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L |
Reset |
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SV01604
1998 May 20 |
3 |
Philips Semiconductors |
Product specification |
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8-bit addressable latch |
74LV259 |
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FUNCTION TABLE
OPERATING MODES |
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INPUTS |
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OUTPUTS |
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MR |
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LE |
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D |
A0 |
A1 |
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A2 |
Q0 |
Q1 |
Q2 |
Q3 |
Q4 |
Q5 |
Q6 |
Q7 |
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Master reset |
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L |
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H |
X |
X |
X |
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X |
L |
L |
L |
L |
L |
L |
L |
L |
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L |
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L |
d |
L |
L |
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L |
Q=d |
L |
L |
L |
L |
L |
L |
L |
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L |
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L |
d |
H |
L |
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L |
L |
Q=d |
L |
L |
L |
L |
L |
L |
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Demultiplex |
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L |
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L |
d |
L |
H |
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L |
L |
L |
Q=d |
L |
L |
L |
L |
L |
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L |
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L |
d |
H |
H |
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L |
L |
L |
L |
Q=d |
L |
L |
L |
L |
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(active HIGH) |
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decoder |
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L |
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L |
d |
L |
L |
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H |
L |
L |
L |
L |
Q=d |
L |
L |
L |
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(when D = H) |
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L |
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L |
d |
H |
L |
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H |
L |
L |
L |
L |
L |
Q=d |
L |
L |
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L |
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L |
d |
L |
H |
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H |
L |
L |
L |
L |
L |
L |
Q=d |
L |
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L |
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L |
d |
H |
H |
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H |
L |
L |
L |
L |
L |
L |
L |
Q=d |
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Store (do nothing) |
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H |
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H |
X |
X |
X |
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X |
q0 |
q1 |
q2 |
q3 |
q4 |
q5 |
q6 |
q7 |
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H |
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L |
d |
L |
L |
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L |
Q=d |
q1 |
q2 |
q3 |
q4 |
q5 |
q6 |
q7 |
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H |
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L |
d |
H |
L |
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L |
q0 |
Q=d |
q2 |
q3 |
q4 |
q5 |
q6 |
q7 |
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H |
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L |
d |
L |
H |
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L |
q0 |
q1 |
Q=d |
q3 |
q4 |
q5 |
q6 |
q7 |
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Addressable latch |
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H |
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L |
d |
H |
H |
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L |
q0 |
q1 |
q2 |
Q=d |
q4 |
q5 |
q6 |
q7 |
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H |
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L |
d |
L |
L |
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H |
q0 |
q1 |
q2 |
q3 |
Q=d |
q5 |
q6 |
q7 |
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H |
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L |
d |
H |
L |
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H |
q0 |
q1 |
q2 |
q3 |
q4 |
Q=d |
q6 |
q7 |
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H |
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L |
d |
L |
H |
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H |
q0 |
q1 |
q2 |
q3 |
q4 |
q5 |
Q=q |
q7 |
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H |
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L |
d |
H |
H |
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H |
q0 |
q1 |
q2 |
q3 |
q4 |
q5 |
q6 |
Q=d |
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NOTES: |
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H |
= |
HIGH voltage level |
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L |
= |
LOW voltage level |
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X |
= |
don't care |
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transition |
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d |
= |
HIGH or LOW data one set-up time prior to the LOW-to-HIGH |
LE |
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q= lower case letters indicate the state of the referenced output established during the last cycle established during the last cycle in which it was addressed or cleared
RECOMMENDED OPERATING CONDITIONS
SYMBOL |
PARAMETER |
CONDITIONS |
MIN |
TYP |
MAX |
UNIT |
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VCC |
DC supply voltage |
See Note 1 |
1.0 |
3.3 |
3.6 |
V |
VI |
Input voltage |
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0 |
± |
VCC |
V |
VO |
Output voltage |
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0 |
± |
VCC |
V |
Tamb |
Operating ambient temperature range in free air |
See DC and AC |
±40 |
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+85 |
°C |
characteristics |
±40 |
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+125 |
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VCC = 1.0V to 2.0V |
± |
± |
500 |
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tr, tf |
Input rise and fall times |
VCC = 2.0V to 2.7V |
± |
± |
200 |
ns/V |
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VCC = 2.7V to 3.6V |
± |
± |
100 |
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NOTE:
1. The LV is guaranteed to function down to VCC = 1.0V (input levels GND or VCC); DC characteristics are guaranteed from VCC = 1.2V to VCC = 5.5V.
1998 May 20 |
4 |
Philips Semiconductors |
Product specification |
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8-bit addressable latch |
74LV259 |
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ABSOLUTE MAXIMUM RATINGS1, 2
In accordance with the Absolute Maximum Rating System (IEC 134).
Voltages are referenced to GND (ground = 0 V).
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PARAMETER |
CONDITIONS |
RATING |
UNIT |
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VCC |
DC supply voltage |
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±0.5 to +4.6 |
V |
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"IIK |
DC input diode current |
VI < ±0.5 or VI > VCC + 0.5V |
20 |
mA |
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"IOK |
DC output diode current |
VO < ±0.5 or VO > VCC + 0.5V |
50 |
mA |
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"IO |
DC output source or sink current |
±0.5V < VO < VCC + 0.5V |
25 |
mA |
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± standard outputs |
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"IGND, |
DC VCC or GND current for types with |
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50 |
mA |
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± standard outputs |
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"ICC |
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Tstg |
Storage temperature range |
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±65 to +150 |
°C |
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Power dissipation per package |
for temperature range: ±40 to +125°C |
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PTOT |
± plastic DIL |
above +70°C derate linearly with 12 mW/K |
750 |
mW |
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± plastic mini-pack (SO) |
above +70°C derate linearly with 8 mW/K |
500 |
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± plastic shrink mini-pack (SSOP and TSSOP) |
above +60°C derate linearly with 5.5 mW/K |
400 |
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NOTES:
1.Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under ªrecommended operating conditionsº is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
2.The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
DC ELECTRICAL CHARACTERISTICS
Over recommended operating conditions. Voltages are referenced to GND (ground = 0 V).
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LIMITS |
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SYMBOL |
PARAMETER |
TEST CONDITIONS |
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-40°C to +85°C |
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-40°C to +125°C |
UNIT |
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MIN |
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TYP1 |
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MAX |
MIN |
MAX |
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HIGH level Input |
VCC = 1.2 V |
0.9 |
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0.9 |
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VIH |
VCC = 2.0 V |
1.4 |
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1.4 |
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V |
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voltage |
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VCC = 2.7 to 3.6 V |
2.0 |
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2.0 |
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LOW level Input |
VCC = 1.2 V |
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0.3 |
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0.3 |
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VIL |
VCC = 2.0 V |
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0.6 |
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0.6 |
V |
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voltage |
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VCC = 2.7 to 3.6 V |
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0.8 |
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0.8 |
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VCC = 1.2 V; VI = VIH or VIL; ±IO = 100μA |
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1.2 |
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VOH |
HIGH level output |
VCC = 2.0 V; VI = VIH or VIL; ±IO = 100μA |
1.8 |
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2.0 |
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1.8 |
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V |
voltage; all outputs |
VCC = 2.7 V; VI = VIH or VIL; ±IO = 100μA |
2.5 |
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2.7 |
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2.5 |
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VCC = 3.0 V; VI = VIH or VIL; ±IO = 100μA |
2.8 |
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3.0 |
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2.8 |
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HIGH level output |
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VOH |
voltage; |
VCC = 3.0 V; VI = VIH or VIL; ±IO = 6mA |
2.40 |
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2.82 |
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2.20 |
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V |
STANDARD |
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outputs |
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VCC = 1.2 V; VI = VIH or VIL; IO = 100μA |
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0 |
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VOL |
LOW level output |
VCC = 2.0 V; VI = VIH or VIL; IO = 100μA |
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0 |
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0.2 |
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0.2 |
V |
voltage; all outputs |
VCC = 2.7 V; VI = VIH or VIL; IO = 100μA |
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0 |
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0.2 |
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0.2 |
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VCC = 3.0 V; VI = VIH or VIL; IO = 100μA |
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0 |
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0.2 |
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0.2 |
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LOW level output |
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VOL |
voltage; |
VCC = 3.0 V; VI = VIH or VIL; IO = 6mA |
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0.25 |
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0.40 |
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0.50 |
V |
STANDARD |
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outputs |
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1998 May 20 |
5 |
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