Philips 74LV257PW, 74LV257N, 74LV257DB, 74LV257D Datasheet

INTEGRATED CIRCUITS

74LV257

Quad 2-input multiplexer (3-State)

Product specification

1998 May 20

Supersedes data of 1997 Jun 06

IC24 Data Handbook

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Philips Semiconductors	Product specification
Quad 2-input multiplexer (3-State)	74LV257

FEATURES

•Optimized for low voltage applications: 1.0 to 3.6 V

•Accepts TTL input levels between VCC = 2.7 V and VCC = 3.6 V

•Typical VOLP (output ground bounce) < 0.8 V at VCC = 3.3 V, Tamb = 25°C

•Typical VOHV (output VOH undershoot) > 2 V at VCC = 3.3 V, Tamb = 25°C

•Non-inverting data path

•Output capability: bus driver

•ICC category: MSI

QUICK REFERENCE DATA

GND = 0 V; Tamb = 25°C; tr = tf ≤ 2.5 ns

DESCRIPTION

The 74LV257 is a low-voltage Si-gate CMOS device and is pin and function compatible with 74HC/HCT257.

The 74LV257 is a quad 2-input multiplexer with 3-state outputs, which select 4 bits of data from two sources and are controlled by a common data select input (S). The data inputs from source 0 (1l0 to 4l0) are selected when input S is LOW and the data inputs from source 1 (1l1 to 4l1) are selected when S in HIGH. Data appears at the outputs (1Y to 4Y) in true (non-inverting) from the selected inputs. The 74LV257 is the logic implementation of a 4-pole, 2-position switch, where the position of the switch is determined by the logic levels applied to S.

The outputs are forced to a high impedance OFF-state when OE is HIGH.

The logic equations for the outputs are:

1Y = OE × (1l1 × S + 1l0 × S)

2Y = OE × (2l1 × S + 2l0 × S) 3Y = OE × (3l1 × S + 3l0 × S) 4Y = OE × (4l1 × S + 4l0 × S)

SYMBOL	PARAMETER	CONDITIONS	TYPICAL	UNIT
	Propagation delay	CL = 15 pF;
tPHL/tPLH	nl0, nl1 to nY	VCC = 3.3 V	10	ns
	S to nY		14
CI	Input capacitance		3.5	pF
CPD	Power dissipation capacitance per gate	VI = GND to VCC1	30	pF

NOTE:

1.CPD is used to determine the dynamic power dissipation (PD in mW) PD = CPD × VCC2 × fi (CL × VCC2 × fo) where:

fi = input frequency in MHz; CL = output load capacitance in pF;

fo = output frequency in MHz; VCC = supply voltage in V;(CL × VCC2 × fo) = sum of the outputs.

ORDERING INFORMATION

PACKAGES	TEMPERATURE RANGE	OUTSIDE NORTH AMERICA	NORTH AMERICA	PKG. DWG. #
16-Pin Plastic DIL	±40°C to +125°C	74LV257 N	74LV257 N	SOT38-4
16-Pin Plastic SO	±40°C to +125°C	74LV257 D	74LV257 D	SOT109-1
16-Pin Plastic SSOP Type II	±40°C to +125°C	74LV257 DB	74LV257 DB	SOT338-1
16-Pin Plastic TSSOP Type I	±40°C to +125°C	74LV257 PW	74LV257PW DH	SOT403-1

PIN CONFIGURATION

PIN DESCRIPTION

PIN

SYMBOL

FUNCTION

S

1

16

VCC

NUMBER

1

S

Common data select input

1I0

2

15

OE

2, 5, 11, 14

1l0 to 4l0

Data inputs from source 0

1I1

3

14

4l0

3, 6, 10, 13

1l1 to 4l1

Data inputs from source 1

IY

4

13

4l1

4, 7, 9, 12

1Y to 4Y

3-state multiplexer outputs

2l0

5

12

4Y

8

GND

Ground (0 V)

2l1

6

11

3l0

3-State output enable input

15

OE

(active LOW)

2Y

7

10

3l1

16

VCC

Positive supply voltage

GND

8

9

3Y

SV00636

1998 May 20

2

853-1985 19420

Philips Semiconductors	Product specification
Quad 2-input multiplexer (3-State)	74LV257

LOGIC SYMBOL												FUNCTIONAL DIAGRAM
		2	3	5	6	11	10	14	13
													2
															1I0							1Y	4
		1I0	11I	2I0	2I1	3I0	3I1	4I0	4I1				3		1I1
1		S											5		2I0							2Y	7
15		OE											6		2I1
																				3±STATE
																	SELECTOR
											11									MULTIPLEXER
				1Y	2Y	3Y	4Y								3I0					OUTPUTS			9
																						3Y
											10				3I1
				4	7	9	12
								SV00637			14				4I0							4Y	12
											13				4I1

LOGIC SYMBOL (IEEE/IEC)						S		OE
1	G1					1		15	SV00639
15	EN
			FUNCTION TABLE
2	1	MUX				INPUTS			OUTPUTS
		4
3				OE		S	nl0	nl1	nY
	1
5				H		X	X	X	Z
6		7		L		H	X	L	L
				L		H	X	H	H
11				L		L	L	X	L
10		9		L		L	H	X	H
			NOTES:
14			H	=	HIGH voltage level
13		12	L	=	LOW voltage level
			X	=	don't care
		SV00638	Z	=	high impedance OFF-state
LOGIC DIAGRAM
1I1		1Y
1I0
2I1		2Y
2I0
3I1		3Y
3I0
4I1		4Y
4I0
OE
S
		SV00640
1998 May 20			3

Philips Semiconductors	Product specification
Quad 2-input multiplexer (3-State)	74LV257

RECOMMENDED OPERATING CONDITIONS

	SYMBOL	PARAMETER	CONDITIONS	MIN	TYP	MAX	UNIT
	VCC	DC supply voltage	See Note 1	1.0	3.3	3.6	V
	VI	Input voltage		0	±	VCC	V
	VO	Output voltage		0	±	VCC	V
	Tamb	Operating ambient temperature range in free air	See DC and AC	±40		+85	°C
			characteristics	±40		+125
			VCC = 1.0V to 2.0V	±	±	500
	tr, tf	Input rise and fall times	VCC = 2.0V to 2.7V	±	±	200	ns/V
			VCC = 2.7V to 3.6V
				±	±	100

NOTE:

1. The LV is guaranteed to function down to VCC = 1.0V (input levels GND or VCC); DC characteristics are guaranteed from VCC = 1.2V to VCC =3.6V.

ABSOLUTE MAXIMUM RATINGS1, 2

In accordance with the Absolute Maximum Rating System (IEC 134).

Voltages are referenced to GND (ground = 0 V).

	SYMBOL	PARAMETER	CONDITIONS	RATING	UNIT
	VCC	DC supply voltage		±0.5 to +4.6	V
	"IIK	DC input diode current	VI < ±0.5 or VI > VCC + 0.5V	20	mA
	"IOK	DC output diode current	VO < ±0.5 or VO > VCC + 0.5V	50	mA
	"IO	DC output source or sink current	±0.5V < VO < VCC + 0.5V	35	mA
		± bus driver outputs
	"IGND,	DC VCC or GND current for types with		70	mA
		± bus driver outputs
	"ICC
	Tstg	Storage temperature range		±65 to +150	°C
		Power dissipation per package	for temperature range: ±40 to +125°C
	PTOT	± plastic DIL	above +70°C derate linearly with 12 mW/K	750	mW
		± plastic mini-pack (SO)	above +70°C derate linearly with 8 mW/K	500
		± plastic shrink mini-pack (SSOP and TSSOP)	above +60°C derate linearly with 5.5 mW/K	400

NOTES:

1.Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under ªrecommended operating conditionsº is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

2.The input and output voltage ratings may be exceeded if the input and output current ratings are observed.

1998 May 20

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