Philips 74lv175 DATASHEETS
INTEGRATED CIRCUITS
74LV175
Quad D-type flip-flop with reset;
positive-edge trigger
Product specification
Supersedes data of 1997 Feb 19
IC24 Data Handbook
1998 May 20
Philips Semiconductors Product specification
74L V175Quad D-type flip-flop with reset; positive-edge trigger
FEA TURES
•Optimized for low voltage applications: 1.0 to 3.6 V
•Accepts TTL input levels between V
•Typical V
T
amb
•Typical V
T
amb
(output ground bounce) < 0.8 V at V
OLP
= 25°C
(output VOH undershoot) > 2 V at V
OHV
= 25°C
= 2.7 V and V
CC
CC
CC
CC
= 3.3 V,
= 3.3 V,
•Four edge-triggered D flip-flops
•Output capability: standard
•I
category: MSI
CC
QUICK REFERENCE DATA
GND = 0 V; T
= 25°C; tr = t
amb
SYMBOL
Propagation delay
t
PHL/tPLH
f
max
C
I
C
PD
CP to Q
MR to Q
Maximum clock frequency 77 MHz
Input capacitance 3.5 pF
Power dissipation capacitance per flip-flop
NOTE:
is used to determine the dynamic power dissipation (PD in µW)
1. C
PD
P
= CPD V
D
= input frequency in MHz; CL = output load capacitance in pF;
f
i
f
= output frequency in MHz; VCC = supply voltage in V;
o
V
(C
L
2
fi (CL V
CC
2
fo) = sum of the outputs.
CC
≤ 2.5 ns
f
PARAMETER CONDITIONS TYPICAL UNIT
Q
n,
n
Q
n,
n
2
fo) where:
CC
= 3.6 V
CL = 15 pF;
VCC = 3.3 V
VCC = 3.3 V
VI = GND to V
DESCRIPTION
The 74LV175 is a low-voltage Si-gate CMOS device and is pin and
function compatible with 74HC/HCT175.
The 74LV175 has four edge-triggered, D-type flip-flops with
individual D inputs and both Q and Q
(CP) and master reset (MR
) inputs load and reset (clear) all flip-flops
simultaneously .
The register is fully edge-triggered. The state of each D input, one
set-up time prior to the LOW-to-HIGH clock transition, is transferred
to the corresponding output (Q
All Qn outputs will be forced LOW independently of clock or data
inputs by a LOW voltage level on the MR
The device is useful for applications where both the true and
complement outputs are required and the clock and master reset are
common to all storage elements.
1
CC
outputs. The common clock
) of the flip-flop.
n
input.
16
14
32 pF
ns
ns
ORDERING INFORMATION
PACKAGES TEMPERATURE RANGE OUTSIDE NORTH AMERICA NORTH AMERICA PKG. DWG. #
16-Pin Plastic DIL –40°C to +125°C 74LV175 N 74LV175 N SOT38-4
16-Pin Plastic SO –40°C to +125°C 74LV175 D 74LV175 D SOT109-1
16-Pin Plastic SSOP Type II –40°C to +125°C 74LV175 DB 74LV175 DB SOT338-1
16-Pin Plastic TSSOP Type I –40°C to +125°C 74LV175 PW 74LV175PW DH SOT403-1
PIN CONFIGURATION
1
MR
2
Q
0
3
Q
0
4
D
0
5
D
1
6
Q
1
7
Q
1
8
GND
1998 May 20 853–1926 19422
16
15
14
13
12
11
10
9
SV00596
V
Q
Q
D
D
Q
Q
CP
CC
3
3
3
2
2
2
PIN DESCRIPTION
PIN
NUMBER
1 MR Master reset input (active LOW)
2, 7, 10, 15 Q0 to Q3Flip-flop outputs
3, 6, 11, 14 Q0 to Q3Complementary flip-flop outputs
4, 5, 12, 13 D0 to D3Data inputs
8 GND Ground (0 V)
9 CP
16 V
2
SYMBOL FUNCTION
Clock input
(LOW-to-HIGH, edge-triggered)
CC
Positive supply voltage
Philips Semiconductors Product specification
OPERATING MODES
74LV175Quad D-type flip-flop with reset; positive-edge trigger
LOGIC SYMBOL (IEEE/IEC)
9
C1
1
R
4
1D
5
12
13
LOGIC SYMBOL
CP
D
4
0
D
5
1
D
12
13
2
D
3
MR
SV00601
9
1
Q
0
Q
0
Q
1
Q
1
Q
2
Q
2
Q
3
Q
3
SV00600
FUNCTIONAL DIAGRAM
Q
4
D
0
2
3
7
6
10
11
15
14
2
3
7
6
10
11
15
14
5
D
1
FF0
12
13
1
9
to
D
FF3
2
D
3
CP
MR
Q
Q
Q
Q
Q
Q
Q
0
0
1
1
2
2
3
3
SV00602
2
3
7
6
10
11
15
14
LOGIC DIAGRAM
MR
CP
D
0
Q
D
FF0 FF2FF1 FF3
CP
Q QQ Q
R
D
Q
D
1
R
D
Q
0
0
Q
D
2
QQ Q
DD D
CPCP CP
R
D
Q
1
1
Q
D
3
R
D
Q
2
2
Q3Q
3
SV00603
FUNCTION TABLE
INPUTS OUTPUTS
MR CP D
n
Reset (clear) L X X L H
Load ‘1’ H ↑ h H L
Load ‘0’ H ↑ l L H
NOTES:
H = HIGH voltage level
h = HIGH voltage level one set-up time prior to the LOW-to-HIGH clock transition
L = LOW voltage level
I = LOW voltage level level one set-up time prior to the LOW-to-HIGH clock transition
↑ = LOW-to-HIGH clock transition
X = don’t care
Q
n
Q
n
1998 May 20
3
Philips Semiconductors Product specification
P
mW
74LV175Quad D-type flip-flop with reset; positive-edge trigger
RECOMMENDED OPERATING CONDITIONS
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNIT
V
V
V
T
amb
tr, t
NOTE:
1. The LV is guaranteed to function down to V
DC supply voltage See Note 1 1.0 3.3 3.6 V
CC
Input voltage 0 – V
I
Output voltage 0 – V
O
Operating ambient temperature range in free air
Input rise and fall times
f
CC
See DC and AC
characteristics
VCC = 1.0V to 2.0V
VCC = 2.0V to 2.7V
V
= 2.7V to 3.6V
CC
= 1.0V (input levels GND or VCC); DC characteristics are guaranteed from VCC = 1.2V to VCC = 3.6V.
–40
–40
–
–
–
–
–
–
–
CC
CC
+85
+125
500
200
100
V
V
°C
ns/V
ABSOLUTE MAXIMUM RATINGS
1, 2
In accordance with the Absolute Maximum Rating System (IEC 134).
Voltages are referenced to GND (ground = 0V).
SYMBOL
V
CC
±I
IK
±I
OK
±I
O
±I
GND
±I
CC
T
stg
DC supply voltage –0.5 to +4.6 V
DC input diode current VI < –0.5 or VI > VCC + 0.5V 20 mA
DC output diode current VO < –0.5 or VO > VCC + 0.5V 50 mA
DC output source or sink current
– standard outputs
DC VCC or GND current for types with
,
–standard outputs
Storage temperature range –65 to +150 °C
PARAMETER CONDITIONS RATING UNIT
–0.5V < VO < VCC + 0.5V 25 mA
50 mA
Power dissipation per package for temperature range: –40 to +125°C
–plastic DIL above +70°C derate linearly with 12mW/K 750
tot
–plastic mini-pack (SO) above +70°C derate linearly with 8 mW/K 500
–plastic shrink mini-pack (SSOP and TSSOP) above +60°C derate linearly with 5.5 mW/K 400
NOTES:
1. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the
device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to
absolute-maximum-rated conditions for extended periods may affect device reliability .
2. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
1998 May 20
4
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