Philips 74LV174PW, 74LV174N, 74LV174DB, 74LV174D Datasheet

INTEGRATED CIRCUITS

74LV174

Hex D-type flip-flop with reset; positive-edge trigger

Product specification

1998 May 20

Supersedes data of 1997 Apr 07

IC24 Data Handbook

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Philips Semiconductors	Product specification
Hex D-type flip-flop with reset; positive edge-trigger	74LV174

FEATURES

•Wide operating voltage: 1.0 to 5.5V

•Optimized for Low Voltage applications: 1.0 to 3.6V

•Accepts TTL input levels between VCC = 2.7V and VCC = 3.6V

•Typical VOLP (output ground bounce) 0.8V @ VCC = 3.3V, Tamb = 25°C

•Typical VOHV (output VOH undershoot) 2V @ VCC = 3.3V, Tamb = 25°C

•Output capability: standard

•ICC category: MSI

DESCRIPTION

The 74LV174 is a low±voltage Si±gate CMOS device and is pin and function compatible with the 74HC/HCT174.

The 74LV174 has six edge±triggered D±type flip±flops with individual D inputs and Q outputs. The common clock (CP) and master reset (MR) inputs load and reset (clear) all flip±flops simultaneously.

The register is fully edge±triggered. The state of each D input, one set±up time prior to the LOW±to±HIGH clock transition, is transferred to the corresponding output of the flip±flop.

A LOW level on the MR input forces all outputs LOW, independently of clock or data inputs.

The device is useful for applications requiring true outputs only and clock and master reset inputs that are common to all storage elements.

QUICK REFERENCE DATA

GND = 0V; Tamb = 25°C; tr = tf 2.5 ns

SYMBOL			PARAMETER	CONDITIONS	TYPICAL	UNIT
		Propagation delay		CL = 15pF	16
t /t		CP to Q				ns
PHL PLH			n	VCC = 3.3V	13
		MR to Qn
fmax		Maximum clock frequency			77	MHz
CI		Input capacitance			3.5	pF
CPD		Power dissipation capacitance per flip-flop		VCC = 3.3V	17	pF
				Notes 1 and 2

NOTES:

1.CPD is used to determine the dynamic power dissipation (PD in μW) PD = CPD VCC2 x fi (CL VCC2 fo) where:

fi = input frequency in MHz; CL = output load capacitance in pF;

fo = output frequency in MHz; VCC = supply voltage in V;(CL VCC2 fo) = sum of the outputs.

2.The condition is VI = GND to VCC

ORDERING INFORMATION

PACKAGES	TEMPERATURE RANGE	OUTSIDE NORTH AMERICA	NORTH AMERICA	PKG. DWG. #
16-Pin Plastic DIL	±40°C to +125°C	74LV174 N	74LV174 N	SOT38-4
16-Pin Plastic SO	±40°C to +125°C	74LV174 D	74LV174 D	SOT109-1
16-Pin Plastic SSOP Type II	±40°C to +125°C	74LV174 DB	74LV174 DB	SOT338-1
16-Pin Plastic TSSOP	±40°C to +125°C	74LV174 PW	74LV174PW DH	SOT403-1

1998 May 20

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853±1964 19422

Philips Semiconductors																							Product specification
Hex D-type flip-flop with reset; positive edge-trigger																							74LV174
PIN CONFIGURATION											LOGIC SYMBOL
															9
		MR			1			16	VCC								CP
		Q0			2			15	Q5		3					D0			Q0				2
		D0			3			14	D5		4					D1			Q1				5
											6								Q2
		D1			4			13	D4							D2							7
		Q1									11					D3			Q3				10
					5			12	Q4
		D2							D3		13					D4			Q4				12
					6			11
		Q2							Q3		14					D5			Q5				15
					7			10
																	MR
	GND				8			9	CP
															1
							SV00347															SV00348
PIN DESCRIPTION											LOGIC SYMBOL (IEEE/IEC)
PIN		SYMBOL						FUNCTION
NUMBER
							Asynchronous master reset (active
1					MR
							LOW)
2, 5, 7, 10,		Q0 to Q5					Flip-flop outputs						9
12, 15																C1
											1
3, 4, 6, 11,		D0 to D5					Data inputs									R
13, 14
8				GND			Ground (0V)				3											2
															1D
9					CP		Clock input (LOW-to-HIGH, edge-				4											5
							triggered)
												6										7
16				VCC			Positive supply voltage
												11										10
											13											12
											14											15
																						SV00349

1998 May 20

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Philips Semiconductors	Product specification
Hex D-type flip-flop with reset; positive edge-trigger	74LV174

FUNCTIONAL DIAGRAM

	3	D0				Q0	2
	4	D1				Q1	5
	6	D2			FF1	Q2	7
	11	D3			to	Q3	10
					FF6
	13	D4				Q4	12
	14	D5				Q5	15
	1
			MR
	9	CP

FUNCTION TABLE

	OPERATING MODES					INPUTS		OUTPUTS
				MR		CP	Dn	Q0
	Reset (clear)			L		X	X	L
		Load `1'		H		↑	h	H
		Load `0'		H		↑	l	L
H	=	HIGH voltage level
h	= HIGH voltage level one set-up time prior to the
		LOW-to-HIGH CP transition
L	=	LOW voltage level

l= LOW voltage level one set-up time prior to the LOW-to-HIGH CP transition

q	= Lower case letter indicates the state of referenced input
	one set-up time prior to the LOW-to-HIGH CP transition

↑= LOW±to±HIGH clock transition

SV00350

RECOMMENDED OPERATING CONDITIONS

	SYMBOL	PARAMETER	CONDITIONS	MIN	TYP.	MAX	UNIT
	VCC	DC supply voltage	See Note1	1.0	3.3	5.5	V
	VI	Input voltage		0	±	VCC	V
	VO	Output voltage		0	±	VCC	V
	Tamb	Operating ambient temperature range in free	See DC and AC	±40		+85	°C
		air	characteristics	±40		+125
			VCC = 1.0V to 2.0V	±	±	500
	tr, tf	Input rise and fall times	VCC = 2.0V to 2.7V	±	±	200	ns/V
			VCC = 2.7V to 3.6V		±	100
				±
			VCC = 3.6V to 5.5V		±	50

NOTES:

1. The LV is guaranteed to function down to VCC = 1.0V (input levels GND or VCC); DC characteristics are guaranteed from VCC = 1.2V to VCC = 5.5V.

1998 May 20

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Philips Semiconductors	Product specification
Hex D-type flip-flop with reset; positive edge-trigger	74LV174

ABSOLUTE MAXIMUM RATINGS1, 2

In accordance with the Absolute Maximum Rating System (IEC 134)

Voltages are referenced to GND (ground = 0V)

SYMBOL	PARAMETER	CONDITIONS	RATING	UNIT
VCC	DC supply voltage		±0.5 to +7.0	V
±IIK	DC input diode current	VI < ±0.5 or VI > VCC + 0.5V	20	mA
±IOK	DC output diode current	VO < ±0.5 or VO > VCC + 0.5V	50	mA
±IO	DC output source or sink current	±0.5V < VO < VCC + 0.5V	25	mA
	± standard outputs
±IGND,	DC VCC or GND current for types with		50	mA
	±standard outputs
±ICC
Tstg	Storage temperature range		±65 to +150	°C
	Power dissipation per package	for temperature range: ±40 to +125°C
PTOT	±plastic DIL	above +70°C derate linearly with 12mW/K	750	mW
	±plastic mini-pack (SO)	above +70°C derate linearly with 8 mW/K	500
	±plastic shrink mini-pack (SSOP and TSSOP)	above +60°C derate linearly with 5.5 mW/K	400

NOTES:

1.Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under ªrecommended operating conditionsº is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

2.The input and output voltage ratings may be exceeded if the input and output current ratings are observed.

DC CHARACTERISTICS FOR THE LV FAMILY

Over recommended operating conditions voltages are referenced to GND (ground = 0V)

						LIMITS
SYMBOL	PARAMETER	TEST CONDITIONS		-40°C to +85°C			-40°C to +125°C		UNIT
			MIN		TYP1	MAX	MIN	MAX
		VCC = 1.2V	0.9				0.9
VIH	HIGH level Input	VCC = 2.0V	1.4				1.4		V
	voltage	VCC = 2.7 to 3.6V	2.0				2.0
		VCC = 4.5 to 5.5V	0.7*VCC				0.7*VCC
		VCC = 1.2V				0.3		0.3
VIL	LOW level Input	VCC = 2.0V				0.6		0.6	V
	voltage	VCC = 2.7 to 3.6V				0.8		0.8
		VCC = 4.5 to 5.5				0.3*VCC		0.3*VCC
		VCC = 1.2V; VI = VIH or VIL; ±IO = 100μA			1.2
	HIGH level output	VCC = 2.0V; VI = VIH or VIL; ±IO = 100μA	1.8		2.0		1.8
		VCC = 2.7V; VI = VIH or VIL; ±IO = 100μA	2.5		2.7		2.5		V
	voltage; all outputs
VOH		VCC = 3.0V; VI = VIH or VIL; ±IO = 100μA	2.8		3.0		2.8
		VCC = 4.5V;VI = VIH or VIL; ±IO = 100μA	4.3		4.5		4.3
	HIGH level output	VCC = 3.0V;VI = VIH or VIL; ±IO = 6mA	2.40		2.82		2.20
	voltage;								V
	STANDARD	VCC = 4.5V;VI = VIH or VIL; ±IO = 12mA	3.60		4.20		3.50
	outputs
		VCC = 1.2V; VI = VIH or VIL; IO = 100μA			0
	LOW level output	VCC = 2.0V; VI = VIH or VIL; IO = 100μA			0	0.2		0.2
		VCC = 2.7V; VI = VIH or VIL; IO = 100μA			0	0.2		0.2	V
	voltage; all outputs
VOL		VCC = 3.0V;VI = VIH or VIL; IO = 100μA			0	0.2		0.2
		VCC = 4.5V;VI = VIH or VIL; IO = 100μA			0	0.2		0.2
	LOW level output	VCC = 3.0V;VI = VIH or VIL; IO = 6mA			0.25	0.40		0.50
	voltage;								V
	STANDARD	VCC = 4.5V;VI = VIH or VIL; IO = 12mA			0.35	0.55		0.65
	outputs

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