Philips 74LV174PW, 74LV174N, 74LV174DB, 74LV174D Datasheet

INTEGRATED CIRCUITS

74LV174

Hex D-type flip-flop with reset; positive-edge trigger

Product specification Supersedes data of 1997 Apr 07 IC24 Data Handbook

 

1998 May 20

Philips Semiconductors Product specification

Hex D-type flip-flop with reset; positive edge-trigger

FEA TURES

•Wide operating voltage: 1.0 to 5.5V

•Optimized for Low Voltage applications: 1.0 to 3.6V

•Accepts TTL input levels between V

•Typical V

T

amb

•Typical V

T

amb

(output ground bounce)  0.8V @ VCC = 3.3V,

OLP

= 25°C

(output VOH undershoot)  2V @ VCC = 3.3V,

OHV

= 25°C

= 2.7V and VCC = 3.6V

CC

•Output capability: standard

•I

category: MSI

CC

QUICK REFERENCE DATA

GND = 0V; T

SYMBOL

t

PHL/tPLH

f

max

C

I

C

PD

NOTES:

1. C

is used to determine the dynamic power dissipation (PD in µW)

PD

= CPD  V

P

D

= input frequency in MHz; CL = output load capacitance in pF;

f

i

f

= output frequency in MHz; VCC = supply voltage in V;

o

 (C

2. The condition is V

= 25°C; tr = tf 2.5 ns

amb

CC

2

 V

L

 fo) = sum of the outputs.

CC

PARAMETER CONDITIONS TYPICAL UNIT

Propagation delay CP to Q

n

MR to Q

n

Maximum clock frequency 77 MHz Input capacitance 3.5 pF

Power dissipation capacitance per flip-flop

2

x fi  (CL  V

= GND to V

I

CC

2

 fo) where:

CC

DESCRIPTION

The 74LV174 is a low–voltage Si–gate CMOS device and is pin and function compatible with the 74HC/HCT174.

The 74LV174 has six edge–triggered D–type flip–flops with individual D inputs and Q outputs. The common clock (CP) and master reset (MR) inputs load and reset (clear) all flip–flops simultaneously .

The register is fully edge–triggered. The state of each D input, one set–up time prior to the LOW–to–HIGH clock transition, is transferred to the corresponding output of the flip–flop.

A LOW level on the MR input forces all outputs LOW, independently of clock or data inputs.

The device is useful for applications requiring true outputs only and clock and master reset inputs that are common to all storage elements.

CL = 15pF VCC = 3.3V

VCC = 3.3V Notes 1 and 2

74L V174

16 13

17 pF

ns

ORDERING INFORMATION

PACKAGES TEMPERATURE RANGE OUTSIDE NORTH AMERICA NORTH AMERICA PKG. DWG. #

16-Pin Plastic DIL –40°C to +125°C 74LV174 N 74LV174 N SOT38-4 16-Pin Plastic SO –40°C to +125°C 74LV174 D 74LV174 D SOT109-1 16-Pin Plastic SSOP Type II –40°C to +125°C 74LV174 DB 74LV174 DB SOT338-1 16-Pin Plastic TSSOP –40°C to +125°C 74LV174 PW 74LV174PW DH SOT403-1

1998 May 20 853–1964 19422

2

Philips Semiconductors Product specification

Hex D-type flip-flop with reset; positive edge-trigger

PIN CONFIGURATION

1

MR

2

Q

0

3

D

0

4

D

1

Q

5

1

D

6

2

Q

2

16

V

15

Q

14

D

13

D

Q

12

D

11

Q

107

98GND CP

SV00347

CC

5

4

3

LOGIC SYMBOL

74LV174

9

CP

3

4

6

11

13

14

D

Q

MR

0

Q

1

Q

2

Q

3

Q

4

Q

5

1

0

1

2

3

4

5

2

5

7

10

12

15

SV00348

PIN DESCRIPTION

NUMBER

1 MR 2, 5, 7, 10,

12, 15 3, 4, 6, 11,

13, 14 8 GND Ground (0V)

9 CP 16 V

SYMBOL FUNCTION

Asynchronous master reset (active LOW)

Q0 to Q

D0 to D

Flip-flop outputs

5

Data inputs

5

Clock input (LOW-to-HIGH, edgetriggered)

CC

Positive supply voltage

LOGIC SYMBOL (IEEE/IEC)

9 1

3

4

6

11

13

14

C1

R

1D

2

5

7

10

12

15

SV00349

1998 May 20

3

Philips Semiconductors Product specification

OPERATING MODES

Hex D-type flip-flop with reset; positive edge-trigger

FUNCTIONAL DIAGRAM

3

D

0

4

D

1

67

D

2

11 10

D

3

13 12

D

4

14 15

D

5

1

MR

9

CP

FF1 FF6

2

Q

0

5

Q

1

Q

2

to

Q

3

Q

4

Q

5

FUNCTION TABLE

Reset (clear) L X X L

Load ‘1’ H ↑ h H Load ‘0’ H ↑ l L

H = HIGH voltage level h = HIGH voltage level one set-up time prior to the

L = LOW voltage level l = LOW voltage level one set-up time prior to the

q = Lower case letter indicates the state of referenced input ↑ = LOW–to–HIGH clock transition

74LV174

INPUTS OUTPUTS

MR CP D

n

LOW-to-HIGH CP transition

LOW-to-HIGH CP transition one set-up time prior to the LOW-to-HIGH CP transition

Q

0

SV00350

RECOMMENDED OPERATING CONDITIONS

SYMBOL PARAMETER CONDITIONS MIN TYP. MAX UNIT

V

CC

V

T

amb

tr, t

NOTES:

1. The LV is guaranteed to function down to V

DC supply voltage See Note1 1.0 3.3 5.5 V Input voltage 0 – V

I

Output voltage 0 – V

O

Operating ambient temperature range in free air

Input rise and fall times

f

= 1.0V (input levels GND or VCC); DC characteristics are guaranteed from VCC = 1.2V to VCC = 5.5V.

CC

See DC and AC characteristics

VCC = 1.0V to 2.0V VCC = 2.0V to 2.7V VCC = 2.7V to 3.6V VCC = 3.6V to 5.5V

–40 –40

– – –

– – – –

CC CC

+85

+125

500 200 100

50

V V

°C

ns/V

1998 May 20

4

Philips Semiconductors Product specification

V

HIGH l

t

voltage all out uts

V

g

V

LOW l

t

voltage all out uts

V

g

V

Hex D-type flip-flop with reset; positive edge-trigger

ABSOLUTE MAXIMUM RATINGS

1, 2

74LV174

In accordance with the Absolute Maximum Rating System (IEC 134) Voltages are referenced to GND (ground = 0V)

SYMBOL

V

CC

±I

IK

±I

OK

±I

O

±I

GND

±I

CC

T

stg

P

TOT

PARAMETER CONDITIONS RATING UNIT

DC supply voltage –0.5 to +7.0 V DC input diode current VI < –0.5 or VI > VCC + 0.5V 20 mA DC output diode current VO < –0.5 or VO > VCC + 0.5V 50 mA DC output source or sink current

– standard outputs DC VCC or GND current for types with

,

–standard outputs

–0.5V < VO < VCC + 0.5V 25 mA

50 mA

Storage temperature range –65 to +150 °C Power dissipation per package

–plastic DIL –plastic mini-pack (SO) –plastic shrink mini-pack (SSOP and TSSOP)

for temperature range: –40 to +125°C above +70°C derate linearly with 12mW/K above +70°C derate linearly with 8 mW/K above +60°C derate linearly with 5.5 mW/K

750 500 400

mW

NOTES:

1. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability .

2. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.

DC CHARACTERISTICS FOR THE LV FAMILY

Over recommended operating conditions voltages are referenced to GND (ground = 0V)

SYMBOL P ARAMETER TEST CONDITIONS

MIN TYP

VCC = 1.2V 0.9 0.9

IH

IL

OH

OL

HIGH level Input voltage

LOW level Input voltage

evel outpu

;

HIGH level output voltage; STANDARD outputs

evel outpu

;

LOW level output voltage; STANDARD outputs

VCC = 2.0V 1.4 1.4 VCC = 2.7 to 3.6V 2.0 2.0 VCC = 4.5 to 5.5V 0.7*V

CC

VCC = 1.2V 0.3 0.3 VCC = 2.0V 0.6 0.6 VCC = 2.7 to 3.6V 0.8 0.8 VCC = 4.5 to 5.5 0.3*V VCC = 1.2V; VI = VIH or V VCC = 2.0V; VI = VIH or V VCC = 2.7V; VI = VIH or V

p

VCC = 3.0V; VI = VIH or V VCC = 4.5V;VI = VIH or V

VCC = 3.0V;VI = VIH or V

VCC = 4.5V;VI = VIH or V VCC = 1.2V; VI = VIH or V

VCC = 2.0V; VI = VIH or V VCC = 2.7V; VI = VIH or V

p

VCC = 3.0V;VI = VIH or V VCC = 4.5V;VI = VIH or V

VCC = 3.0V;VI = VIH or V

VCC = 4.5V;VI = VIH or V

–IO = 100µA 1.2

IL;

–IO = 100µA 1.8 2.0 1.8

IL;

–IO = 100µA 2.5 2.7 2.5

IL;

–IO = 100µA 2.8 3.0 2.8

IL;

–IO = 100µA 4.3 4.5 4.3

IL;

–IO = 6mA 2.40 2.82 2.20

IL;

–IO = 12mA 3.60 4.20 3.50

IL;

IO = 100µA 0

IL;

IO = 100µA 0 0.2 0.2

IL;

IO = 100µA 0 0.2 0.2

IL;

IO = 100µA 0 0.2 0.2

IL;

IO = 100µA 0 0.2 0.2

IL;

IO = 6mA 0.25 0.40 0.50

IL;

IO = 12mA 0.35 0.55 0.65

IL;

LIMITS

-40°C to +85°C -40°C to +125°C

1

MAX MIN MAX

0.7*V

CC

0.3*V

UNIT

CC

V

1998 May 20

5