Philips 74LV165PW, 74LV165N, 74LV165DB, 74LV165D Datasheet

INTEGRATED CIRCUITS

74LV165

8-bit parallel-in/serial-out shift register

Product specification

1998 May 07

Supersedes data of 1997 May 15

IC24 Data Handbook

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Philips Semiconductors	Product specification
8-bit parallel-in/serial-out shift register	74LV165

FEATURES

•Wide operating voltage: 1.0 to 5.5 V

•Optimized for low voltage applications: 1.0 to 3.6 V

•Accepts TTL input levels between VCC = 2.7 V and VCC = 3.6 V

•Typical VOLP (output ground bounce) < 0.8 V at VCC = 3.3 V, Tamb = 25°C

•Typical VOHV (output VOH undershoot) > 2 V at VCC = 3.3 V, Tamb = 25°C

•Asynchronous 8-bit parallel load

•Synchronous serial input

•Output capability: standard

•ICC category: MSI

DESCRIPTION

The 74LV165 is a low-voltage Si-gate CMOS device and is pin and function compatible with 74HC/HCT165.

The 74LV165 is an 8-bit parallel-load or serial-in shift register with complementary serial outputs (Q7 and Q7) available from the last

stage. When the parallel load (PL) input is LOW, parallel data from the D0 to D7 inputs are loaded into the register asynchronously. When PL is HIGH, data enters the register serially at the DS input and shifts one place to the right (Q0→ Q1→ Q2, etc.) with each positive-going clock transition. This feature allows parallel-to-serial converter expansion by tying the Q7 output to the DS input of the succeeding stage.

The clock input is a gated-OR structure which allows one input to be used as an active LOW clock enable (CE) input. The pin assignment for the CP and CE inputs is arbitrary and can be reversed for layout convenience. The LOW-to-HIGH transition of input CE should only take place while CP HIGH for predictable operation. Either the CP or the CE should be HIGH before the LOW-to-HIGH transition of PL to prevent shifting the data when PL is activated.

QUICK REFERENCE DATA

GND = 0 V; Tamb = 25°C; tr = tf ≤ 2.5 ns

SYMBOL

PARAMETER

CONDITIONS

TYPICAL

UNIT

Propagation delay

CL = 15 pF;

tPHL/tPLH

CE,

CP to Q7,

Q

7

VCC = 3.3 V

18

ns

PL

to Q7,

Q

7

18

D7 to Q7,

Q

7

14

fmax

Maximum clock frequency

78

MHz

CI

Input capacitance

3.5

pF

CPD

Power dissipation capacitance per gate

VCC = 3.3 V

35

pF

VI = GND to VCC1

NOTES:

1.CPD is used to determine the dynamic power dissipation (PD in mW) PD = CPD × VCC2 × fi (CL × VCC2 × fo) where:

fi = input frequency in MHz; CL = output load capacitance in pF;

fo = output frequency in MHz; VCC = supply voltage in V;

(CL × VCC2 × fo) = sum of the outputs.

ORDERING INFORMATION

PACKAGES	TEMPERATURE RANGE	OUTSIDE NORTH AMERICA	NORTH AMERICA	PKG. DWG. #
16-Pin Plastic DIL	±40°C to +125°C	74LV165 N	74LV165 N	SOT38-4
16-Pin Plastic SO	±40°C to +125°C	74LV165 D	74LV165 D	SOT109-1
16-Pin Plastic SSOP Type II	±40°C to +125°C	74LV165 DB	74LV165 DB	SOT338-1
16-Pin Plastic TSSOP Type I	±40°C to +125°C	74LV165 PW	74LV165PW DH	SOT403-1

PIN CONFIGURATION

PIN DESCRIPTION

V

PIN NUMBER

SYMBOL

FUNCTION

1

16

PL

CC

1

PL

Asynchronous parallel load

input (active LOW)

CP

2

15

CE

2

CP

Clock input (LOW to

D4

3

14

D3

HIGH, edge-triggered)

D5

4

13

D2

Complementary output from

7

Q7

the last stage

D6

5

12

D1

8

GND

Ground (0 V)

D7

6

11

D0

9

Q7

Serial output from last stage

Q

7

7

10

DS

10

DS

Serial data input

11, 12, 13, 14, 3, 4, 5, 6

D0 to D7

Parallel data inputs

GND

8

9

Q7

Clock enable input

15

CE

SV00585

(active LOW)

16

VCC

Positive supply voltage

1998 May 07

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853±1915 19349

Philips Semiconductors	Product specification
8-bit parallel-in/serial-out shift register	74LV165

LOGIC SYMBOL									FUNCTIONAL DIAGRAM
						10								11		12		13		14		3		4		5		6
				DS
11			D0											D0		D1		D2		D3		D4		D5		D6		D7
12			D1	1
13
			D2								PL

14 D3

3D4

4D5

5					D6			Q7			9	10			D S
6					D7			Q7			7								8±BIT SHIFT REGISTER			Q 7			9
1					PL							2			CP										7
							CE												PARALLEL± IN / SERIAL ± OUT			Q 7
					CP
												15
						2		15							CE
								SV00586
																						SV00588

LOGIC SYMBOL (IEEE/IEC)

	1	SRG8
		C2 [LOAD]
	15	G1 [SHIFT]
		> 1
	2	1 C3/

10

3D

11

2D

12

2D

13

14

3

4

5

9

6

7

SV00587

LOGIC DIAGRAM

	D0	D1	D2	D3	D4	D5	D6	D7
DS
CP	SD	SD	SD	SD	SD	SD	SD	SD	Q
	D Q	D Q	D Q	D Q	D Q	D Q	D Q	D Q	7
CE	CP	CP	CP	CP	CP	CP	CP	CP
PL	FF0	FF1	FF2	FF3	FF4	FF5	FF6	FF7	Q7
	RD	RD	RD	RD	RD	RD	RD	Q
								RD
									SV00589

1998 May 07

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Philips Semiconductors	Product specification
8-bit parallel-in/serial-out shift register	74LV165

FUNCTION TABLE

OPERATING MODES

INPUTS

Qn REGISTERS

OUTPUTS

PL

CE

CP

DS

D0±D7

Q0

Q1±Q6

Q7

Q

7

Parallel load

L

X

X

X

L

L

L±L

L

H

L

X

X

X

H

H

H±H

H

L

H

L

↑

l

X

L

q0±q5

q6

6

Serial Shift

q

H

L

↑

h

X

H

q0±q5

q6

q

6

Hold ªdo nothingº

H

H

X

X

X

q0

q1±q6

q7

q7

NOTES:

H

=

HIGH voltage level

h

= HIGH voltage level one set-up time prior to the LOW-to-HIGH clock transition

L

=

LOW voltage level

I

= LOW voltage level level one set-up time prior to the LOW-to-HIGH clock transition

q

= lower case letters indicate the state of the referenced output one set-up time prior to the LOW-to-HIGH clock transition

X

=

don't care

↑

=

LOW-to-HIGH clock transition

RECOMMENDED OPERATING CONDITIONS

SYMBOL	PARAMETER	CONDITIONS	MIN	TYP	MAX	UNIT
VCC	DC supply voltage	See Note 1	1.0	3.3	5.5	V
VI	Input voltage		0	±	VCC	V
VO	Output voltage		0	±	VCC	V
Tamb	Operating ambient temperature range in free air	See DC and AC	±40		+85	°C
		characteristics	±40		+125
		VCC = 1.0V to 2.0V	±	±	500
tr, tf	Input rise and fall times	VCC = 2.0V to 2.7V	±	±	200	ns/V
		VCC = 2.7V to 3.6V	±	±	100
		VCC = 3.6V to 5.5V	±	±	50

NOTE:

1. The LV is guaranteed to function down to VCC = 1.0V (input levels GND or VCC); DC characteristics are guaranteed from VCC = 1.2V to VCC = 5.5V.

ABSOLUTE MAXIMUM RATINGS1, 2

In accordance with the Absolute Maximum Rating System (IEC 134).

Voltages are referenced to GND (ground = 0 V).

	SYMBOL	PARAMETER	CONDITIONS	RATING	UNIT
	VCC	DC supply voltage		±0.5 to +7.0	V
	"IIK	DC input diode current	VI < ±0.5 or VI > VCC + 0.5V	20	mA
	"IOK	DC output diode current	VO < ±0.5 or VO > VCC + 0.5V	50	mA
	"IO	DC output source or sink current	±0.5V < VO < VCC + 0.5V		mA
		± standard outputs		25
	"IGND,	DC VCC or GND current for types with			mA
		± standard outputs		50
	"ICC
	Tstg	Storage temperature range		±65 to +150	°C
		Power dissipation per package	for temperature range: ±40 to +125°C
	PTOT	± plastic DIL	above +70°C derate linearly with 12 mW/K	750	mW
		± plastic mini-pack (SO)	above +70°C derate linearly with 8 mW/K	500
		± plastic shrink mini-pack (SSOP and TSSOP)	above +60°C derate linearly with 5.5 mW/K	400

NOTES:

1.Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under ªrecommended operating conditionsº is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

2.The input and output voltage ratings may be exceeded if the input and output current ratings are observed.

1998 May 07

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Philips Semiconductors	Product specification
8-bit parallel-in/serial-out shift register	74LV165

DC ELECTRICAL CHARACTERISTICS

Over recommended operating conditions. Voltages are referenced to GND (ground = 0 V).

						LIMITS
SYMBOL	PARAMETER	TEST CONDITIONS		-40°C to +85°C			-40°C to +125°C		UNIT
			MIN		TYP1	MAX	MIN	MAX
		VCC = 1.2 V	0.9				0.9
VIH	HIGH level Input	VCC = 2.0 V	1.4				1.4		V
	voltage	VCC = 2.7 to 3.6 V	2.0				2.0
		VCC = 4.5 to 5.5 V	0.7<VCC				0.7<VCC
		VCC = 1.2 V				0.3		0.3
VIL	LOW level Input	VCC = 2.0 V				0.6		0.6	V
	voltage	VCC = 2.7 to 3.6 V				0.8		0.8
		VCC = 4.5 to 5.5				0.3<VCC		0.3<VCC
		VCC = 1.2 V; VI = VIH or VIL; ±IO = 100μA			1.2
	HIGH level output	VCC = 2.0 V; VI = VIH or VIL; ±IO = 100μA	1.8		2.0		1.8
VOH		VCC = 2.7 V; VI = VIH or VIL; ±IO = 100μA	2.5		2.7		2.5		V
	voltage; all outputs
		VCC = 3.0 V; VI = VIH or VIL; ±IO = 100μA	2.8		3.0		2.8
		VCC = 4.5 V; VI = VIH or VIL; ±IO = 100μA	4.3		4.5		4.3
	HIGH level output	VCC = 3.0 V; VI = VIH or VIL; ±IO = 6mA	2.40		2.82		2.20
	voltage;
VOH									V
	STANDARD	VCC = 4.5 V; VI = VIH or VIL; ±IO = 12mA	3.60		4.20		3.50
	outputs
		VCC = 1.2 V; VI = VIH or VIL; IO = 100μA			0
	LOW level output	VCC = 2.0 V; VI = VIH or VIL; IO = 100μA			0	0.2		0.2
VOL		VCC = 2.7 V; VI = VIH or VIL; IO = 100μA			0	0.2		0.2	V
	voltage; all outputs
		VCC = 3.0 V; VI = VIH or VIL; IO = 100μA			0	0.2		0.2
		VCC = 4.5 V; VI = VIH or VIL; IO = 100μA			0	0.2		0.2
	LOW level output	VCC = 3.0 V; VI = VIH or VIL; IO = 6mA			0.25	0.40		0.50
	voltage;
VOL									V
	STANDARD	VCC = 4.5 V; VI = VIH or VIL; IO = 12mA			0.35	0.55		0.65
	outputs
II	Input leakage	VCC = 5.5 V; VI = VCC or GND				1.0		1.0	μA
	current
ICC	Quiescent supply	VCC = 5.5 V; VI = VCC or GND; IO = 0				20.0		160	μA
	current; MSI
	Additional								μA
ICC	quiescent supply	VCC = 2.7 V to 3.6 V; VI = VCC ± 0.6 V				500		850
	current per input

NOTE:

1. All typical values are measured at Tamb = 25°C.

1998 May 07

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