Philips 74lv163 DATASHEETS
INTEGRATED CIRCUITS
74LV163
Presettable synchronous 4-bit binary
counter; synchronous reset
Product specification
Supersedes data of 1997 May 15
IC24 Data Handbook
1998 Apr 30
Philips Semiconductors Product specification
Presettable synchronous 4-bit binary counter;
synchronous reset
FEA TURES
•Optimized for low voltage applications: 1.0 to 3.6 V
•Accepts TTL input levels between V
•Typical V
T
amb
•Typical V
T
amb
(output ground bounce) < 0.8 V at V
OLP
= 25°C
(output VOH undershoot) > 2 V at V
OHV
= 25°C
= 2.7 V and V
CC
CC
CC
= 3.6 V
CC
= 3.3 V,
= 3.3 V,
•Synchronous counting and loading
•Two count enable inputs for n-bit cascading
•Positive-edge triggered clock
•Synchronous reset
•Output capability: standard
•I
category: MSI
CC
DESCRIPTION
The 74LV163 is a low-voltage Si-gate CMOS device and is pin and
function compatible with 74HC/HCT163.
The 74LV163 is a synchronous presettable binary counter which
features an internal look-head carry and can be used for high-speed
counting. Synchronous operation is provided by having all flip-flops
clocked simultaneously on the positive-going edge of the clock (CP).
The outputs (Q
LOW level. A LOW level at the parallel enable input (PE
counting action and causes the data at the data inputs (D
loaded into the counter on the positive-going edge of the clock
(providing that the set-up and hold time requirements for PE
Preset takes place regardless of the levels at count enable inputs
(CEP and CET). A low level at the master reset input (MR
four outputs of the flip-flops (Q
positive-going transition on the clock (CP) input (provided that the
set-up and hold time requirements for MR are met).
This action occurs regardless of the levels at PE, CET and CEP
inputs. This synchronous reset feature enables the designer to
modify the maximum count with only one external NAND gate. The
look ahead carry simplifies serial cascading of the counters. Both
count enable inputs (CEP and CET) must be HIGH to count. The
CET input is fed forward to enable the terminal count output (TC).
The TC output thus enabled will produce a HIGH output pulse of a
duration approximately equal to a HIGH level output of Q
pulse can be used to enable the next cascading stage. The
maximum clock frequency for the cascaded counters is determined
by the CP to TC propagation delay and CEP to CP set-up time,
according to the following formula:
f
max
to Q3) of the counters may be preset to a HIGH or
0
to Q3) to LOW level after the next
0
(CP to TC) tsu(CEP to CP)
tp
(max)
1
74L V163
) disables the
to D3) to be
0
are met).
) sets all
. This
0
QUICK REFERENCE DATA
GND = 0 V; T
SYMBOL
t
PHL/tPLH
f
max
C
I
C
PD
NOTES:
is used to determine the dynamic power dissipation (PD in µW)
1. C
PD
P
= CPD × V
D
= input frequency in MHz; CL = output load capacitance in pF;
f
i
f
= output frequency in MHz; VCC = supply voltage in V;
o
(C
L
= 25°C; tr = t
amb
Propagation delay
CP to Q
CP to TC
CET to TC
Maximum clock frequency 77 MHz
Input capacitance 3.5 pF
Power dissipation capacitance per gate VI = GND to V
2
× fi (CL × V
CC
2
× V
× fo) = sum of the outputs.
CC
≤ 2.5 ns
f
PARAMETER CONDITIONS TYPICAL UNIT
CL = 15 pF;
n
2
× fo) where:
CC
VCC = 3.3 V
CC
1
15
18
9
25 pF
ns
ORDERING INFORMATION
PACKAGES TEMPERATURE RANGE OUTSIDE NORTH AMERICA NORTH AMERICA PKG. DWG. #
16-Pin Plastic DIL –40°C to +125°C 74LV163 N 74LV163 N SOT38-4
16-Pin Plastic SO –40°C to +125°C 74LV163 D 74LV163 D SOT109-1
16-Pin Plastic SSOP Type II –40°C to +125°C 74LV163 DB 74LV163 DB SOT338-1
16-Pin Plastic TSSOP Type I –40°C to +125°C 74LV163 PW 74LV163PW DH SOT403-1
1998 Apr 30 853–1916 19318
2
Philips Semiconductors Product specification
Presettable synchronous 4-bit binary counter;
synchronous reset
PIN CONFIGURATION
1
MR
2
CP
3
D
0
4
D
1
5
D
2
6
D
3
7
CEP
8
GND
PIN DESCRIPTION
PIN NUMBER SYMBOL FUNCTION
1
2 CP
3, 4, 5, 6 D0 to D3Data inputs
7 CEP Count enable inputs
8 GND Ground (0 V)
9 PE Parallel enable input (active LOW)
10 CET Count enable carry input
14, 13, 12, 11 Q0 to Q3Flip-flop outputs
15 TC Terminal count output
16 V
MR Asynchronous master reset
(active LOW)
Clock input
(LOW-to-HIGH, edge-triggered)
CC
Positive supply voltage
16
15
14
13
12
11
10
9
SV00569
V
CC
TC
Q
Q
Q
Q
CET
PE
0
1
2
3
LOGIC SYMBOL
D
3
4
5
6
9
D
D
D
PE
0
1
2
3
FUNCTIONAL DIAGRAM
D
0
9
PE
10
CET
7
CEP
CP
2
1
MR
PARALLEL LOAD
CIRCUITRY
COUNTER
Q
0
14
15
TC
CPCETCEP
21071
D
D
1
BINARY
Q
Q
1
Q
Q
Q
Q
MR
6115124133
D
2
3
Q
2
3
74LV163
14
0
13
1
12
2
11
3
SV00570
TC
SV00572
15
LOGIC SYMBOL (IEEE/IEC)
R
M1
G3
G4
1, 2D
CTR4
C2/1,3,4+
4CT = 15
1
9
7
10
2
3
4
5
6
1998 Apr 30
14
13
12
11
15
SV00571
3
Philips Semiconductors Product specification
OPERATING MODES
Parallel load
Hold (do nothing)
Presettable synchronous 4-bit binary counter;
74LV163
synchronous reset
FUNCTION TABLE
INPUTS OUTPUTS
MR CP CEP CET PE D
n
Reset (clear) l ↑ X X X X L L
h ↑ X X I I L L
h ↑ X X I h H *
Count h ↑ h h h X Count *
h X I X h X q
h X X I h X q
NOTES:
* = The TC output is HIGH when CET is HIGH and the counter is at terminal count (HHHH)
H = HIGH voltage level
h = HIGH voltage level one set-up time prior to the LOW-to-HIGH clock transition
L = LOW voltage level
I = LOW voltage level level one set-up time prior to the LOW-to-HIGH clock transition
q = lower case letters indicate the state of the referenced output one set-up time prior to the LOW-to-HIGH clock transition
X = don’t care
↑ = LOW-to-HIGH clock transition
STATE DIAGRAM
0 1 2 3 4
15
14
13
12
5
6
7
891011
SV00573
TYPICAL TIMING SEQUENCE
MR
PE
D
0
D
1
D
2
D
3
CP
CEP
CET
Q
0
Q
1
Q
2
Q
3
TC
Typical timing sequence: reset outputs to zero; preset to binary twelve; count to
thirteen, fourteen, fifteen, zero, one and two; inhibit
13 14 15 0 1 2
12
resetpreset count inhibit
Q
n
n
n
SV00582
TC
*
L
1998 Apr 30
4
Philips Semiconductors Product specification
Presettable synchronous 4-bit binary counter;
synchronous reset
LOGIC DIAGRAM
CET
CEP
PE
D
0
D
1
74LV163
D
2
D
3
MR
CP
FF0 FF1 FF2 FF3
QQQQ
DDDD
CP
Q
Q
0
CP CP CP
Q Q Q
Q
1
Q
2
Q3TC
SV00583
1998 Apr 30
5
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