Philips 74HCT574U, 74HCT574PW, 74HCT574N, 74HCT574DB, 74HCT574D Datasheet
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INTEGRATED CIRCUITS
DATA SHEET
For a complete data sheet, please also download:
∙The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications
∙The IC06 74HC/HCT/HCU/HCMOS Logic Package Information
∙The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines
74HC/HCT574
Octal D-type flip-flop; positive edge-trigger; 3-state
Product specification |
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December 1990 |
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File under Integrated Circuits, IC06 |
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Philips Semiconductors |
Product specification |
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Octal D-type flip-flop; positive
74HC/HCT574
edge-trigger; 3-state
FEATURES
·3-state non-inverting outputs for bus oriented applications
·8-bit positive edge-triggered register
·Common 3-state output enable input
·Independent register and 3-state buffer operation
·Output capability: bus driver
·ICC category: MSI
QUICK REFERENCE DATA
GND = 0 V; Tamb = 25 °C; tr = tf = 6 ns
GENERAL DESCRIPTION
The 74HC/HCT574 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A.
The 74HC/HCT574 are octal D-type flip-flops featuring separate D-type inputs for each flip-flop and non-inverting 3-state outputs for bus oriented applications. A clock (CP)
and an output enable (OE) input are common to all flip-flops.
The 8 flip-flops will store the state of their individual D-inputs that meet the set-up and hold time requirements on the LOW-to-HIGH CP transition.
When OE is LOW, the contents of the 8 flip-flops are available at the outputs.
When OE is HIGH, the outputs go to the high impedance OFF-state. Operation of the OE input does not affect the state of the flip-flops.
The “574” is functionally identical to the “564”, but has non-inverting outputs.
The “574” is functionally identical to the “374”, but has a different pinning.
SYMBOL |
PARAMETER |
CONDITIONS |
TYPICAL |
UNIT |
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HC |
HCT |
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tPHL/ tPLH |
propagation delay CP to Qn |
CL = 15 pF; VCC = 5 V |
14 |
15 |
ns |
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fmax |
maximum clock frequency |
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123 |
76 |
MHz |
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CI |
input capacitance |
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3.5 |
3.5 |
pF |
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CPD |
power dissipation capacitance per flip-flop |
notes 1 and 2 |
22 |
25 |
pF |
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Notes
1. CPD is used to determine the dynamic power dissipation (PD in mW): PD = CPD ´ VCC2 ´ fi + å (CL ´ VCC2 ´ fo) where:
fi = input frequency in MHz
fo = output frequency in MHz
å (CL ´ VCC2 ´ fo) = sum of outputs
CL = output load capacitance in pF
VCC = supply voltage in V
2. For HC the condition is VI = GND to VCC
For HCT the condition is VI = GND to VCC - 1.5 V
ORDERING INFORMATION
See “74HC/HCT/HCU/HCMOS Logic Package Information”.
December 1990 |
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Philips Semiconductors |
Product specification |
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Octal D-type flip-flop; positive edge-trigger;
74HC/HCT574
3-state
PIN DESCRIPTION
PIN NO. |
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SYMBOL |
NAME AND FUNCTION |
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1 |
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3-state output enable input (active LOW) |
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OE |
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2, 3, 4, 5, 6, 7, 8, 9 |
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D0 to D7 |
data inputs |
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10 |
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GND |
ground (0 V) |
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11 |
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CP |
clock input (LOW-to-HIGH, edge-triggered) |
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19, 18, 17, 16, 15, 14, 13, 12 |
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Q0 to Q7 |
3-state flip-flop outputs |
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20 |
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VCC |
positive supply voltage |
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Fig.1 Pin configuration. |
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Fig.2 Logic symbol. |
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Fig.3 IEC logic symbol. |
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December 1990 |
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