Philips 74HCT573U, 74HCT573PW, 74HCT573NB, 74HCT573N, 74HCT573DB Datasheet
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INTEGRATED CIRCUITS
DATA SHEET
For a complete data sheet, please also download:
∙The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications
∙The IC06 74HC/HCT/HCU/HCMOS Logic Package Information
∙The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines
74HC/HCT573
Octal D-type transparent latch; 3-state
Product specification |
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December 1990 |
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File under Integrated Circuits, IC06 |
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Philips Semiconductors |
Product specification |
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Octal D-type transparent latch; 3-state |
74HC/HCT573 |
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FEATURES
·Inputs and outputs on opposite sides of package allowing easy interface with microprocessors
·Useful as input or output port for microprocessors/microcomputers
·3-state non-inverting outputs for bus oriented applications
·Common 3-state output enable input
·Functionally identical to the “563” and “373”
·Output capability: bus driver
·ICC category: MSI
QUICK REFERENCE DATA
GND = 0 V; Tamb = 25 °C; tr = tf = 6 ns
GENERAL DESCRIPTION
The 74HC/HCT573 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A.
The 74HC/HCT573 are octal D-type transparent latches featuring separate D-type inputs for each latch and 3-state outputs for bus oriented applications.
A latch enable (LE) input and an output enable (OE) input are common to all latches.
The “573” consists of eight D-type transparent latches with 3-state true outputs. When LE is HIGH, data at
the Dn inputs enter the latches. In this condition the latches are transparent, i.e. a latch output will change state each time its corresponding D-input changes.
When LE is LOW the latches store the information that was present at the D-inputs a set-up time preceding the HIGH-to-LOW transition of LE. When OE is LOW, the contents of the 8 latches are available at the outputs. When OE is HIGH, the outputs go to the high impedance OFF-state. Operation of the OE input does not affect the state of the latches.
The “573” is functionally identical to the “563” and “373”, but the “563” has inverted outputs and the “373” has a different pin arrangement.
SYMBOL |
PARAMETER |
CONDITIONS |
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TYPICAL |
UNIT |
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HC |
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HCT |
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tPHL/ tPLH |
propagation delay |
CL = 15 pF; VCC = 5 V |
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Dn to Qn |
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14 |
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17 |
ns |
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LE to Qn |
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15 |
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15 |
ns |
CI |
input capacitance |
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3.5 |
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3.5 |
pF |
CPD |
power dissipation capacitance per latch |
notes 1 and 2 |
26 |
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26 |
pF |
Notes
1. CPD is used to determine the dynamic power dissipation (PD in mW): PD = CPD ´ VCC2 ´ fi +å (CL ´ VCC2 ´ fo) where:
fi = input frequency in MHz; fo = output frequency in MHz
å (CL ´ VCC2 ´ fo) = sum of outputs
CL = output load capacitance in pF; VCC = supply voltage in V
2. For HC the condition is VI = GND to VCC; for HCT the condition is VI = GND to VCC - 1.5 V
ORDERING INFORMATION
See “74HC/HCT/HCU/HCMOS Logic Package Information”.
December 1990 |
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Philips Semiconductors |
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Product specification |
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Octal D-type transparent latch; 3-state |
74HC/HCT573 |
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PIN DESCRIPTION |
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PIN NO. |
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SYMBOL |
NAME AND FUNCTION |
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2, 3, 4, 5, 6, 7, 8, 9 |
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D0 to D7 |
data inputs |
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11 |
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LE |
latch enable input (active HIGH) |
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1 |
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3-state output enable input (active LOW) |
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OE |
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10 |
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GND |
ground (0 V) |
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19, 18, 17, 16, 15, 14, 13, 12 |
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Q0 to Q7 |
3-state latch outputs |
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20 |
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VCC |
positive supply voltage |
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Fig.1 Pin configuration. |
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Fig.2 Logic symbol. |
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Fig.3 IEC logic symbol. |
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December 1990 |
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