Philips 74HCT40103U, 74HCT40103N, 74HCT40103DB, 74HCT40103D, 74HC40103D Datasheet

INTEGRATED CIRCUITS

DATA SHEET

For a complete data sheet, please also download:

∙The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications

∙The IC06 74HC/HCT/HCU/HCMOS Logic Package Information

∙The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines

74HC/HCT40103

8-bit synchronous binary down counter

Product specification

1998 Jul 08

Supersedes data of December 1990

File under Integrated Circuits, IC06

Philips Semiconductors	Product specification
8-bit synchronous binary down counter	74HC/HCT40103

FEATURES

·Cascadable

·Synchronous or asynchronous preset

·Output capability: standard

·ICC category: MSI

GENERAL DESCRIPTION

The 74HC/HCT40103 are high-speed Si-gate CMOS devices and are pin compatible with the “40103” of the “4000B” series. They are specified in compliance with JEDEC standard no. 7A.

The 74HC/HCT40103 consist each of an 8-bit synchronous down counter with a single output which is active when the internal count is zero. The “40103” contains a single 8-bit binary counter and has control inputs for enabling or disabling the clock (CP), for clearing the counter to its maximum count, and for presetting the counter either synchronously or asynchronously. All control inputs and the terminal count output (TC) are active-LOW logic.

In normal operation, the counter is decremented by one count on each positive-going transition of the clock (CP).

QUICK REFERENCE DATA

GND = 0 V; Tamb = 25 °C; tr = tf = 6 ns

Counting is inhibited when the terminal enable input (TE) is HIGH. The terminal count output (TC) goes LOW when the count reaches zero if TE is LOW, and remains LOW for one full clock period.

When the synchronous preset enable input (PE) is LOW, data at the jam input (P0 to P7) is clocked into the counter on the next positive-going clock transition regardless of the state of TE. When the asynchronous preset enable input (PL) is LOW, data at the jam input (P0 to P7) is asynchronously forced into the counter regardless of the state of PE, TE, or CP. The jam inputs (P0 to P7) represent a single 8-bit binary word.

When the master reset input (MR) is LOW, the counter is asynchronously cleared to its maximum count (decimal 255) regardless of the state of any other input. The precedence relationship between control inputs is indicated in the function table.

If all control inputs except TE are HIGH at the time of zero count, the counters will jump to the maximum count, giving a counting sequence of 256 clock pulses long.

The “40103” may be cascaded using the TE input and the TC output, in either a synchronous or ripple mode.

	SYMBOL	PARAMETER			CONDITIONS	TYPICAL		UNIT
						HC	HCT
	tPHL/ tPLH	propagation delay CP to			CL = 15 pF; VCC = 5 V	30	30	ns
			TC
	fmax	maximum clock frequency				32	31	MHz
	CI	input capacitance				3.5	3.5	pF
	CPD	power dissipation capacitance per package			notes 1 and 2	24	27	pF

Notes

1. CPD is used to determine the dynamic power dissipation (PD in mW): PD = CPD ´ VCC2 ´ fi + å (CL ´ VCC2 ´ fo) where:

fi = input frequency in MHz

fo = output frequency in MHz

å (CL ´ VCC2 ´ fo) = sum of outputs

CL = output load capacitance in pF

VCC = supply voltage in V

2. For HC the condition is VI = GND to VCC

For HCT the condition is VI = GND to VCC - 1.5 V

1998 Jul 08

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Philips Semiconductors										Product specification
8-bit synchronous binary down counter										74HC/HCT40103
ORDERING INFORMATION
TYPE NUMBER									PACKAGE
	NAME								DESCRIPTION		VERSION
74HC40103N;	DIP16							plastic dual in-line package; 16 leads (300 mil); long body			SOT38-1
74HCT40103N
74HC40103D;	SO16							plastic small outline package; 16 leads; body width 3.9 mm			SOT109-1
74HCT40103D
74HC40103DB;	SSOP16							plastic shrink small outline package; 16 leads; body width 5.3 mm			SOT338-1
74HCT40103DB
74HC40103PW;	TSSOP16							plastic thin shrink small outline package; 16 leads; body width 4.4 mm			SOT403-1
PIN DESCRIPTION
PIN NO.			SYMBOL						NAME AND FUNCTION
1			CP						clock input (LOW-to-HIGH, edge-triggered)
2									asynchronous master reset input (active LOW)
			MR
3									terminal enable input
			TE
4, 5, 6, 7, 10, 11, 12, 13			P0 to P7						jam inputs
8			GND						ground (0 V)
9									asynchronous preset enable input (active LOW)
			PL
14									terminal count output (active LOW)
			TC
15									synchronous preset enable input (active LOW)
			PE
16			VCC						positive supply voltage

Fig.1 Pin configuration.		Fig.2 Logic symbol.		Fig.3 IEC logic symbol.

1998 Jul 08

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Philips Semiconductors	Product specification
8-bit synchronous binary down counter	74HC/HCT40103

Fig.4 Functional diagram.

FUNCTION TABLE

CONTROL INPUTS

PRESET MODE

ACTION

MR

PL

PE

TE

H

H

H

H

inhibit counter

H

H

H

L

synchronous

count down

H

H

L

X

preset on next LOW-to HIGH clock transition

H

L

X

X

asynchronous

preset asynchronously

L

X

X

X

clear to maximum count

Note

1.Clock connected to CP.

Synchronous operation: changes occur on the LOW-to-HIGH CP transition.

Jam inputs: MSD = P7, LSD = P0. H = HIGH voltage level

L = LOW voltage level X = don’t care

APPLICATIONS

∙Divide-by-n counters

∙Programmable timers

∙Interrupt timers

∙Cycle/program counters

1998 Jul 08

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Philips Semiconductors	Product specification
8-bit synchronous binary down counter	74HC/HCT40103

Fig.5 Logic diagram.

Fig.6	Timing diagram.
1998 Jul 08	5

Philips Semiconductors	Product specification
8-bit synchronous binary down counter	74HC/HCT40103
DC CHARACTERISTICS FOR 74HC
For the DC characteristics see “74HC/HCT/HCU/HCMOS Logic Family Specifications”.
Output capability: standard
ICC category: MSI

AC CHARACTERISTICS FOR 74HC

GND = 0 V; tr = tf = 6 ns; CL = 50 pF

																					Tamb (°C)						TEST CONDITIONS
SYMBOL	PARAMETER																					74HC				UNIT		WAVEFORMS
																											VCC
																			+25			−40 to +85		−40 to +125
																											(V)
																		min.	typ.	max.		min.	max.	min.	max.
tPHL/ tPLH	propagation delay																		96	300			375		450	ns	2.0	Fig.7
		CP to								TC									35	60			75		90		4.5
																			28	51			64		77		6.0
tPHL/ tPLH	propagation delay																		50	175			220		265	ns	2.0	Fig.8
		TE					to		TC										18	35			44		53		4.5
																			14	30			37		45		6.0
tPHL/ tPLH	propagation delay																		102	315			395		475	ns	2.0	Fig.9
		PL				to		TC											37	63			79		95		4.5
																			30	53			40		81		6.0
tPHL	propagation delay																		83	275			345		415	ns	2.0	Fig.9
		MR					to				TC								30	55			69		83		4.5
																			24	47			59		71		6.0
tTHL/ tTLH	output transition time																		19	75			95		110	ns	2.0	Figs 7 and 8
																			7	15			19		22		4.5
																			6	13			16		19		6.0
tW	clock pulse width																	165	22			205		250		ns	2.0	Fig.7
		HIGH or LOW																33	8			41		50			4.5
																		28	6			35		43			6.0
tW	master reset pulse width																	125	39			155		190		ns	2.0	Fig.9
		LOW																25	14			31		38			4.5
																		21	11			26		32			6.0
tW	preset enable pulse width																	125	33			155		190		ns	2.0	Fig.9
		PL;				LOW												25	12			31		38			4.5
																		21	10			26		32			6.0
trem	removal time																	50	14			65		75		ns	2.0	Fig.10
		MR					to CP or									PL	to CP	10	5			13		15			4.5
																		9	4			11		13			6.0
tsu	set-up time																	75	22			95		110		ns	2.0	Fig.11
		PE				to CP												15	8			19		22			4.5
																		13	6			16		19			6.0

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