Philips 74hc t00 DATASHEETS

INTEGRATED CIRCUITS

DATA SH EET

For a complete data sheet, please also download:

•The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications

•The IC06 74HC/HCT/HCU/HCMOS Logic Package Information

•The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines

74HC/HCT00

Quad 2-input NAND gate

Product specification
File under Integrated Circuits, IC06

December 1990

Philips Semiconductors Product specification

Quad 2-input NAND gate 74HC/HCT00

FEATURES

• Output capability: standard

• ICC category: SSI

GENERAL DESCRIPTION

The 74HC/HCT00 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL).
They are specified in compliance with JEDEC standard no. 7A.

The 74HC/HCT00 provide the 2-input NAND function.

QUICK REFERENCE DATA

GND = 0 V; T

= 25 °C; tr= tf= 6 ns

amb

SYMBOL PARAMETER CONDITIONS

t

PHL

C
C

I
PD

/ t

PLH

propagation delay nA, nB to nY CL= 15 pF; VCC=5V 7 10 ns
input capacitance 3.5 3.5 pF
power dissipation capacitance per gate notes 1 and 2 22 22 pF

Notes

1. C

is used to determine the dynamic power dissipation (PDin µW):

PD

PD= CPD× V

2

× fi+ ∑ (CL× V

CC

2

× fo) where:

CC

fi= input frequency in MHz
fo= output frequency in MHz
CL= output load capacitance in pF
VCC= supply voltage in V
Σ (CL× V

2. For HC the condition is VI= GND to V

2

× fo) = sum of outputs

CC

CC

For HCT the condition is VI= GND to VCC− 1.5 V

ORDERING INFORMATION

See

“74HC/HCT/HCU/HCMOS Logic Package Information”

.

TYPICAL

UNIT

HC HCT

December 1990 2