Philips 74hc hct7597 DATASHEETS

INTEGRATED CIRCUITS

DATA SH EET

For a complete data sheet, please also download:

•The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications

•The IC06 74HC/HCT/HCU/HCMOS Logic Package Information

•The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines

74HC/HCT7597

8-bit shift register with input latches

Product specification
File under Integrated Circuits, IC06

December 1990

Philips Semiconductors Product specification

8-bit shift register with input latches 74HC/HCT7597

FEATURES

• 8-bit parallel input latches

• Shift register has direct overriding load and clear

• Output capability: standard

• ICCcategory: MSI

The 74HC/HCT7597 both consist of an 8-bit storage latch
feeding a parallel-in, serial-out 8-bit shift register.

LE is LOW, data at the Dninputs enter the latches.

When
In this condition the latches are transparent, i.e. a latch
output will change state each time its corresponding
D-input changes.

When LE is HIGH the latches store the information that

GENERAL DESCRIPTION

The 74HC/HCT7597 are high-speed Si-gate CMOS
devices and are pin compatible with low power Schottky
TTL (LSTTL). They are specified in compliance with

was present at the D-inputs, a set-up time preceding the
LOW-to-HIGH transition of LE.

The shift register has a positive edge-triggered clock,
direct load (from storage) and clear inputs.

JEDEC standard no. 7A.

QUICK REFERENCE DATA

GND = 0 V; T

=25°C; tr=tf= 6 ns

amb

SYMBOL PARAMETER CONDITIONS

t

PHL

/ t

PLH

propagation delay CL= 15 pF; VCC= 5 V

to Q 15 17 ns

SH

CP

LE to Q 22 27 ns
PL to Q 20 23 ns

to Q 20 24 ns

D

7

f

max

C
C

I
PD

maximum clock frequency SH

CP

input capacitance 3.5 3.5 pF
power dissipation capacitance per package notes 1, 2 29 30 pF

TYPICAL

UNIT

HC HCT

99 79 MHz

Notes

1. C

is used to determine the dynamic power dissipation (PDin µW):

PD

PD=CPD× V

2

× fi+∑(CL× V

CC

2

× fo) where:

CC

fi= input frequency in MHz; fo= output frequency in MHz
∑ (CL× V

2

× fo) = sum of outputs

CC

CL= output load capacitance in pF; VCC= supply voltage in V

2. For HC the condition is VI= GND to VCC; for HCT the condition is VI= GND to VCC− 1.5 V

ORDERING INFORMATION

“74HC/HCT/HCU/HCMOS Logic Package Information”

See

.

December 1990 2

Philips Semiconductors Product specification

8-bit shift register with input latches 74HC/HCT7597

PIN DESCRIPTION

PIN NO. SYMBOL NAME AND FUNCTION

8 GND ground (0 V)
9 Q serial data output
10
11 SH
12
13
14 D
15, 1, 2, 3, 4, 5, 6, 7 D
16 V

MR asynchronous reset input (active LOW)

CP

shift clock input (LOW-to-HIGH, edge-triggered)
LE latch enable input (active LOW)
PL parallel load input (active LOW)

S
0
CC

to D

7

serial data input

parallel data inputs

positive supply voltage

Fig.1 Pin configuration. Fig.2 Logic symbol. Fig.3 IEC logic symbol.

December 1990 3

Philips Semiconductors Product specification

8-bit shift register with input latches 74HC/HCT7597

FUNCTION TABLE

LE SHCPPL MR FUNCTION

L X X X data enabled to input latches (transparent)
H X X X data stored into latches (non-transparent)
X X L H data transferred from input latches to shift register
X X L L invalid logic, state of shift register indeterminate when signals removed
X X H L shift register cleared
X ↑ H H shift register clocked Q

Notes

1. H = HIGH voltage level
L = LOW voltage level
X = don’t care
↑ = LOW-to-HIGH CP transition

n=Qn-1

, Q0=D

S

Fig.4 Functional diagram.

December 1990 4