Philips 74hc hct75 DATASHEETS
INTEGRATED CIRCUITS
DATA SH EET
For a complete data sheet, please also download:
•The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications
•The IC06 74HC/HCT/HCU/HCMOS Logic Package Information
•The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines
74HC/HCT75
Quad bistable transparent latch
Product specification
File under Integrated Circuits, IC06
December 1990
Philips Semiconductors Product specification
Quad bistable transparent latch 74HC/HCT75
FEATURES
• Complementary Q and Q outputs
• VCC and GND on the centre pins
• Output capability: standard
• ICC category: MSI
GENERAL DESCRIPTION
The 74HC/HCT75 have four bistable latches. The two
latches are simultaneously controlled by one of two active
HIGH enable inputs (LE
HIGH, the data enters the latches and appears at the nQ
outputs. The nQ outputs follow the data inputs (nD) as long
as LE
is HIGH (transparent). The data on the nD inputs
n-n
one set-up time prior to the HIGH-to-LOW transition of the
LE
will be stored in the latches. The latched outputs
n-n
remain stable as long as the LE
The 74HC/HCT75 are high-speed Si-gate CMOS devices
and are pin compatible with low power Schottky TTL
(LSTTL). They are specified in compliance with JEDEC
standard no. 7A.
QUICK REFERENCE DATA
GND = 0 V; T
=25°C; tr=tf=6ns
amb
SYMBOL PARAMETER CONDITIONS
/ t
t
PHL
PLH
C
I
C
PD
propagation delay CL= 15 pF; VCC=5V
nD to nQ, n
LE
n-n
Q1112ns
to nQ, nQ1111ns
input capacitance 3.5 3.5 pF
power dissipation capacitance per latch notes 1 and 2 42 42 pF
and LE
1-2
TYPICAL
HC HCT
3-4
is LOW.
n-n
). When LE
n-n
UNIT
is
Notes
1. C
is used to determine the dynamic power dissipation (PD in µW):
PD
PD=CPD× V
2
× fi+∑ (CL× V
CC
2
× fo) where:
CC
fi= input frequency in MHz
fo= output frequency in MHz
∑ (CL× V
2
× fo) = sum of outputs
CC
CL= output load capacitance in pF
VCC= supply voltage in V
2. For HC the condition is VI= GND to V
CC
For HCT the condition is VI= GND to VCC−1.5 V
ORDERING INFORMATION
“74HC/HCT/HCU/HCMOS Logic Package Information”
See
.
December 1990 2
Philips Semiconductors Product specification
Quad bistable transparent latch 74HC/HCT75
PIN DESCRIPTION
PIN NO. SYMBOL NAME AND FUNCTION
1, 14, 11, 8 1
2, 3, 6, 7 1D to 4D data inputs
4LE
5V
12 GND ground (0 V)
13 LE
16, 15, 10, 9 1Q to 4Q latch outputs
Q to 4Q complementary latch outputs
3-4
CC
1-2
latch enable input, latches 3 and 4 (active HIGH)
positive supply voltage
latch enable input, latches 1 and 2 (active HIGH)
Fig.1 Pin configuration. Fig.2 Logic symbol. Fig.3 IEC logic symbol.
December 1990 3
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