Philips 74hc hct7404 DATASHEETS

INTEGRATED CIRCUITS

DATA SH EET

For a complete data sheet, please also download:

•The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications

•The IC06 74HC/HCT/HCU/HCMOS Logic Package Information

•The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines

74HC/HCT7404

5-Bit x 64-word FIFO register; 3-state

Product speciﬁcation Supersedes data of October 1990 File under Integrated Circuits, IC06

September 1993

Philips Semiconductors Product speciﬁcation

5-Bit x 64-word FIFO register; 3-state 74HC/HCT7404

FEATURES

• Synchronous or asynchronous operation

• 3-state outputs

• 30 MHz (typical) shift-in and shift-out rates

• Readily expandable in word and bit dimensions

• Pinning arranged for easy board layout: input pins

directly opposite output pins

• Output capability: driver (8 mA)

• ICC category: LSI.

GENERAL DESCRIPTION

The 74HC/HCT7404 are high-speed Si-gate CMOS devices specified in compliance with JEDEC standard no.7A.

The “7404” is an expandable, First-In First-Out (FIFO) memory organized as 64 words by 5 bits. A guaranteed 15 MHz data-rate makes it ideal for high-speed applications. A higher data-rate can be obtained in applications where the status flags are not used (burst-mode).

With separate controls for shift-in (SI) and shift-out (

APPLICATIONS

• High-speed disc or tape controller

• Communications buffer.

reading and writing operations are completely independent, allowing synchronous and asynchronous data transfers. Additional controls include a master-reset input (MR), an output enable input (OE) and flags. The data-in-ready (DIR) and data-out-ready (DOR) flags indicate the status of the device.

QUICK REFERENCE DATA

GND = 0 V; T

= 25 °C; tr = tf = 6 ns.

amb

SYMBOL PARAMETER CONDITIONS

t

PHL/tPLH

f

max

C

I

C

PD

propagation delay SO, SI to DIR and DOR CL = 15 pF; VCC = 5 V 15 17 ns maximum clock frequency 30 30 MHz input capacitance 3.5 3.5 pF power dissipation capacitance per package note 1 475 490 pF

SO),

TYP.

UNIT

HC HCT

Note

1. For HC the condition is V

= GND to VCC.

I

For HCT the condition is VI = GND to VCC−1.5 V.

ORDERING INFORMATION

EXTENDED

TYPE NUMBER

PINS PIN POSITION MATERIAL CODE

PACKAGE

74HC/HCT7404N 18 DIL plastic SOT102 74HC/HCT7404D 20 SO20 plastic SOT163A

September 1993 2

Philips Semiconductors Product speciﬁcation

5-Bit x 64-word FIFO register; 3-state 74HC/HCT7404

PINNING (SOT102)

SYMBOL PIN DESCRIPTION

OE 1 output enable input (active

LOW) DIR 2 data-in-ready output SI 3 shift-in input (active HIGH) D

to D

O

4, 5, 6, 7, 8 parallel data inputs

4

GND 9 ground MR 10 asynchronous master-reset

input (active LOW) Q

to Q

4

0

11, 12, 13,

data outputs

14, 15 DOR 16 data-out-ready output SO 17 shift-out input (active LOW) V

CC

18 positive supply voltage

PINNING (SOT163A)

SYMBOL PIN DESCRIPTION

OE 1 output enable input (active

LOW) DIR 2 data-in-ready output SI 3 shift-in input (active HIGH) n.c. 4 not connected D

to D

0

5, 6, 7, 8, 9 parallel data inputs

4

GND 10 ground MR 11 asynchronous master-reset

input (active LOW) Q

to Q

4

0

12, 13, 14,

data outputs

15, 16 n.c. 17 not connected DOR 18 data-out ready output n.c. 19 not connected V

CC

20 positive supply voltage

handbook, halfpage

OE

DIR

D D D D D

GND

1 2

SI

3 4

0

5

1 2 3 4

7404

6 7 8 9

MGA670

V

18

CC

17

SO DOR

16

Q

15

0

Q

14

1

Q

13

2

Q

12

3

Q

11

4

10

MR

Fig.1 Pin configuration (SOT102).

handbook, halfpage

OE

DIR

n.c.

D D D D D

GND

1

2 3

SI

4 5

0 1 2 3 4

7404

6 7 8 9

10

MGA671

V

20

CC

19

SO

18

DOR

n.c.

17 16

Q

0

Q

15

1

Q

14

2

Q

13

3

Q

12

4

11

MR

Fig.2 Pin configuration (SOT163).

September 1993 3

Philips Semiconductors Product speciﬁcation

5-Bit x 64-word FIFO register; 3-state 74HC/HCT7404

D D

D D D

SI SO

0 1

2 3 4

10 (11)

1 (1)

OE

MR

Q Q

Q Q Q

DOR

DIR

15 (16)

0

14 (15)

1

13 (14)

2

12 (13)

3

11 (12)

4

16 (18)

2 (2)

MGA673

handbook, halfpage

(5) 4 (6) 5 (7) 6 (8) 7 (9) 8

(3) 3

(19) 17

Pin numbers between parentheses refer to the SO package.

Fig.3 Logic symbol.

handbook, halfpage

(1) 1

(3) 3 (11) 10 (19) 17

(5) 4

(6) 5

(7) 6

(8) 7

(9) 8

Pin numbers between parentheses refer to the SO package.

EN4 1Z3

1 ( /C2)

CT = 0

5

5Z6

2D

FIFO 64 x 5

CTR

<

CT 64

CT 0

>

[IR] 3

[OR] 6

G1 G5

4

MGA675

Fig.4 IEC logic symbol.

2 (2) 16 (18)

15 (16) 14 (15) 13 (14) 12 (13) 11 (12)

handbook, full pagewidth

(5) 4

D

0

(6) 5

D

1

(7) 6

D

2

(8) 7

D

INPUT

3

D

MR

4

STAGE

1 x 5 BITS

DIR

(9) 8

(11) 10

Pin numbers between parentheses refer to the SO package.

MAIN FIFO

REGISTER

62 x 5 BITS

CONTROL LOGIC

SI DOR SO

Fig.5 Functional diagram.

September 1993 4

OUTPUT

STAGE

1 x 5 BITS

16 (18)2 (2) 1 (1) 3 (3)

17 (19)

OE

Q

15 (16)

0

14 (15)

Q

1

13 (14)

Q

2

12 (13)

Q

3

11 (12)

Q

4

MGA680

Philips Semiconductors Product speciﬁcation

5-Bit x 64-word FIFO register; 3-state 74HC/HCT7404

DOR

ull pagewidth

SO

FP

(1)

R

SQ

R

61 x

FB

(1)

R

(2)

FF64 R

RQ

to

FF3

FF63

R

RQ

SQ

OE

Q0Q

CL CL

1

3-STATE

5

OUTPUT

LATCHES

Q3Q

BUFFER

4

MSB117

position 64

position 3 to 63

Fig.6 Logic diagram.

(2)

FF2

RQ

SQ

R

(2)

FF1

SQ

RQ

R

FS

MR

(1)

SI

SQ

R

September 1993 5

DIR

5

CL CL

D0D1D3D

LATCHES

5

LATCHES

4

position 2

position 1

LOW on R input of FF1 to FF64 will set Q output to LOW independent of state on S input.

(See control flip-flops)

LOW on S input of flip-flops FS, FB and FP will set Q output to HIGH independent of state on R input.

Philips Semiconductors Product speciﬁcation

5-Bit x 64-word FIFO register; 3-state 74HC/HCT7404

FUNCTIONAL DESCRIPTION

The DIR flag indicates the input stage status, either empty and ready to receive data (DIR = HIGH) or full and busy (DIR = LOW). When DIR and SI are HIGH, data present at D0 to D4 is shifted into the input stage; once complete DIR goes LOW. When SI is set LOW, data is automatically shifted to the output stage or to the last empty location. A FIFO which can receive data is indicated by DIR set HIGH.

A DOR flag indicates the output stage status, either data available (DOR = HIGH) or busy

outputs (Q new data may be shifted into the output stage, once complete DOR is set LOW.

Expanded Format (see Fig.18) The DOR and DIR signals are used to

allow the ‘7404’ to be cascaded. Both parallel and serial expansion is possible. Serial expansion is only possible with typical devices.

Parallel Expansion

Parallel expansion is accomplished by logically ANDing the DOR and DIR signals to form a composite signal.

to Q4). When SO is LOW

0

Serial Expansion

Serial expansion is accomplished by:

• tying the data outputs of the first device to the data inputs of the second device

• connecting the DOR pin of the first device to the SI pin of the second device

• connecting the device to the DIR pin of the second device.

(DOR = LOW). When SO and DOR are HIGH, data is available at the

DC CHARACTERISTICS FOR 74HC

For the DC characteristics see

“74HC/HCT/HCU/HCMOS Logic Family Specifications”

Output capability: parallel outputs, bus driver; serial output, standard ICC category: MSI

SO pin of the first

.

Output capability: driver 8 mA ICC category: LSI Voltages are referenced to GND (ground = 0 V).

DC CHARACTERISTICS FOR 74HC

SYMBOL PARAMETER

+25 −40 to +85 −40 to +125

MIN TYP MAX MIN MAX MIN MAX

V

OH

V

OL

HIGH level output voltage

LOW level output voltage−−

3.98

5.48

4.32

5.81−−

0.15

T

0.26

0.26−−

°C

amb

3.84

5.34−−

0.33

0.33−−

3.70

5.20−−

0.4

UNIT

V V

TEST CONDITION

V

CC

V

or V

I

IH

IL IH

IL

IO = −8 mA IO = −10 mA

IO = 8 mA IO = 10 mA

(V)

4.56V

OTHER

September 1993 6

Philips Semiconductors Product speciﬁcation

5-Bit x 64-word FIFO register; 3-state 74HC/HCT7404

AC CHARACTERISTICS FOR 74HC

GND = 0 V; t

= tf = 6 ns; CL = 50 pF.

r

SYMBOL PARAMETER

t

PHL/tPLH

propagation delay MR to DIR, DOR

t

PHL

propagation delay

t

PHL/tPLH

MR to Q propagation

n

delay SI to DIR

t

PHL/tPLH

propagation delay SO to DOR

t

PHL/tPLH

propagation delay

t

PHL/tPLH

DOR to Q propagation

n

delay

t

PLH

SO to Q propagation

n

delay/ripple through delay SI to DOR

t

PLH

propagation delay/bubble-up delay SO to DIR

t

PZH/tPZL

3-state output enable

t

PHZ/tPLZ

OE to Q 3-state output

n

disable

t

THL/tTLH

OE to Q output transition

n

time

t

W

SI pulse width HIGH or LOW357

t

W

SO pulse width HIGH or LOW7014

°C

T

amb

+25 −40 to +85 −40 to +125

MIN TYP MAX MIN MAX MIN MAX

−

6

12

69 25 20

52 19 15

66 24 19

94 34 27

11 4 3

105 38 30

2.2

0.8

0.6

2.8

1.0

0.8

44 16 13

50 18 14

14 5 4

11 4 3

22 8 6

210 42 36

160 32 27

205 41 35

290 58 49

35 7

6.0 325

65 55

7.0

1.4

1.2

9.0

1.8

1.5

150 30 26

60 12 10

−

45 9 8

90 18 15

265 53 45

200 40 34

255 51 43

365 73 62

45 9 8

406 81 69

8.8

1.8

1.5

11.2

2.2

1.9

190 38 32

190 38 33

75 15 13

−

55 11 9

105 21 18

315 63 54

240 48 41

310 62 53

435 87 74

55 11 9

488 98 83

10.5

2.1

1.8

13.5

2.7

2.3

225 45 38

90 18 15

−

UNIT

ns ns ns

µs µs µs

ns ns ns

TEST CONDITION

V

CC

(V)

2.0

WAVEFORMS

Fig.9

4.5

6.0

2.0

Fig.9

4.5

6.0

2.0

Fig.7

4.5

6.0

2.0

Fig.10

4.5

6.0

2.0

Fig.11

4.5

6.0

2.0

Fig.15

4.5

6.0

2.0

Fig.16

4.5

6.0

2.0

Fig.8

4.5

6.0

2.0

Fig.17

4.5

6.0

2.0

Fig.17

4.5

6.0

2.0

Fig.17

4.5

6.0

2.0

Fig.7

4.5

6.0

2.0

Fig.10

4.5

6.0

September 1993 7

Philips Semiconductors Product speciﬁcation

5-Bit x 64-word FIFO register; 3-state 74HC/HCT7404

T

SYMBOL PARAMETER

t

W

DIR pulse width HIGH

t

W

DOR pulse width HIGH

t

W

MR pulse width LOW

t

rem

removal time MR to SI

t

su

set-up time Dn to SI

t

h

hold time Dn to SI

f

max

maximum clock pulse frequency SI, SO burst mode

f

max

maximum clock pulse frequency SI, SO using ﬂags

f

max

maximum clock pulse frequency SI, SO cascaded

°C

amb

+25 −40 to +85 −40 to +125

MIN TYP MAX MIN MAX MIN MAX

10 5 4

14 7 6

120 24 20

80 16 14

−8

−4

−3

135 27 23

3.6 18 21

−

41 15 12

52 19 15

39 14 11

24 8 7

−36

−13

−10

44 16 13

9.9 30 36

7.6 23 27

130 26 22

160 32 27

−

8 4 3

12 6 5

150 30 26

100 20 17

−6

−3

170 34 29

2.8 14 16

−

165 33 28

200 40 34

−

8 4 3

12 6 5

180 36 31

120 24 20

−6

−3

205 41 35

2.4 12 14

−

195 39 33

240 48 41

−

UNIT

ns ns ns

MHz MHz MHz

TEST CONDITION

V

CC

(V)

2.0

WAVEFORMS

Fig.8

4.5

6.0

2.0

Fig.11

4.5

6.0

2.0

Fig.9

4.5

6.0

2.0

Fig.16

4.5

6.0

2.0

Fig.14

4.5

6.0

2.0

Fig.14

4.5

6.0

2.0

4.5

Fig.12 and Fig.13

6.0

2.0

4.5

Fig.7 and Fig.10

6.0

2.0

4.5

Fig.7 and Fig.10

6.0

September 1993 8

Philips Semiconductors Product speciﬁcation

5-Bit x 64-word FIFO register; 3-state 74HC/HCT7404

DC CHARACTERISTICS FOR 74HCT

For the DC characteristics see

“74HC/HCT/HCU/HCMOS Logic Family Specifications”

, except that VOH and VOL are not

valid for driver output. They are replaced by the values given below. Output capability: driver 8 mA ICC category: LSI. Voltages are referenced to GND (ground = 0 V).

DC CHARACTERISTICS FOR 74HCT

T

SYMBOL PARAMETER

V

OH

HIGH level output voltage

V

OL

LOW level output voltage

°C

amb

+25 −40 to +85 −40 to +125

UNIT

MIN TYP MAX MIN MAX MIN MAX

3.98 4.32 − 3.84 − 3.7 − V 4.5 V

− 0.15 0.26 − 0.33 − 0.40 V 4.5 V

TEST CONDITION

V

CC

V

(V)

IH

or V

IL IH

or V

IL

Note to HCT types

The value of additional quiescent supply current (∆I

) for a unit load of 1 is given in the family specifications.

CC

To determine ∆ICC per input, multiply this value by the unit load coefficient shown in the table below.

I

IO = −8 mA

IO = 8 mA

OTHER

UNIT LOAD COEFFICIENT

INPUT UNIT LOAD COEFFICIENT

OE 1

SI 1.5

D

n

0.75 MR 1.5 SO 1.5

September 1993 9