Philips 74hc hct7046a DATASHEETS

INTEGRATED CIRCUITS

DATA SH EET

For a complete data sheet, please also download:

•The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications

•The IC06 74HC/HCT/HCU/HCMOS Logic Package Information

•The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines

74HC/HCT7046A

Phase-locked-loop with lock
detector

Product specification
File under Integrated Circuits, IC06

December 1990

Philips Semiconductors Product specification

V

Phase-locked-loop with lock detector 74HC/HCT7046A

FEATURES

• Low power consumption

• Centre frequency up to 17 MHz

(typ.) at VCC= 4.5 V

• Choice of two phase comparators:
EXCLUSIVE-OR;
edge-triggered JK flip-flop;

• Excellent VCO frequency linearity

• VCO-inhibit control for ON/OFF

keying and for low standby power
consumption

• Minimal frequency drift

• Operation power supply voltage

range:
VCO section 3.0 to 6.0 V
digital section 2.0 to 6.0 V

• Zero voltage offset due to op-amp
buffering

• Output capability: standard

• ICC category: MSI

GENERAL DESCRIPTION

The 74HC/HCT7046 are high-speed
Si-gate CMOS devices and are
specified in compliance with JEDEC
standard no. 7.

The 74HC/HCT7046 are
phase-locked-loop circuits that
comprise a linear voltage-controlled
oscillator (VCO) and two different
phase comparators (PC1 and PC2)
with a common signal input amplifier
and a common comparator input.

A lock detector is provided and this
gives a HIGH level at pin 1 (LD) when
the PLL is locked. The lock detector
capacitor must be connected
between pin 15 (C

) and pin 8

LD

(GND). The value of the CLD capacitor
can be determined, using information
supplied in Fig.32. The input signal
can be directly coupled to large
voltage signals, or indirectly coupled
(with a series capacitor) to small
voltage signals. A self-bias input
circuit keeps small voltage signals
within the linear region of the input

amplifiers. With a passive low-pass
filter, the “7046” forms a second-order
loop PLL. The excellent VCO linearity
is achieved by the use of linear
op-amp techniques.

VCO

The VCO requires one external
capacitor C1 (between C1

and C1B)

A

and one external resistor R1
(between R1 and GND) or two
external resistors R1 and R2
(between R1 and GND, and R2 and
GND). Resistor R1 and capacitor C1
determine the frequency range of the
VCO. Resistor R2 enables the VCO
to have a frequency offset if required.

The high input impedance of the VCO
simplifies the design of low-pass
filters by giving the designer a wide
choice of resistor/capacitor ranges. In
order not to load the low-pass filter, a
demodulator output of the VCO input
voltage is provided at pin 10
(DEM
techniques where the DEM

). In contrast to conventional

OUT

OUT

voltage is one threshold voltage lower
than the VCO input voltage, here the
DEM
VCO input. If DEM

voltage equals that of the

OUT

is used, a load

OUT

resistor (RS) should be connected
from DEM
DEM

OUT

VCO output (VCO

to GND; if unused,

OUT

should be left open. The

) can be

OUT

connected directly to the comparator
input (COMPIN), or connected via a
frequency-divider. The VCO output
signal has a duty factor of 50%
(maximum expected deviation 1%), if
the VCO input is held at a constant
DC level. A LOW level at the inhibit
input (INH) enables the VCO and
demodulator, while a HIGH level turns
both off to minimize standby power
consumption.

The only difference between the HC
and HCT versions is the input level
specification of the INH input. This
input disables the VCO section. The
comparators’ sections are identical,
so that there is no difference in the

SIG

(pin 14) or COMPIN (pin 3)

IN

inputs between the HC and HCT
versions.

Phase comparators

The signal input (SIG

) can be

IN

directly coupled to the self-biasing
amplifier at pin 14, provided that the
signal swing is between the standard
HC family input logic levels.
Capacitive coupling is required for
signals with smaller swings.

Phase comparator 1 (PC1)

This is an EXCLUSIVE-OR network.
The signal and comparator input
frequencies (fi) must have a 50% duty
factor to obtain the maximum locking
range. The transfer characteristic of
PC1, assuming ripple (f

=2fi) is

r

suppressed,
is:

V

DEMOUT

where V

DEMOUT

CC

---------- -

π

is the demodulator

–()=

φ

SIGINφCOMPIN

V

output at pin 10;
V

DEMOUT=VPC1OUT

(via low-pass

filter).
The phase comparator gain

is:

K

CC

Vr⁄().=

---------- -

p

π

The average output voltage from
PC1, fed to the VCO input via the
low-pass filter and seen at the
demodulator output at pin 10
(V

DEMOUT

), is the resultant of the
phase differences of signals (SIGIN)
and the comparator input (COMPIN)
as shown in Fig.6. The average of
V

DEMOUT

there is no signal or noise at SIG

is equal to 1/2 VCC when

IN

and with this input the VCO oscillates
at the centre frequency (fo). Typical

December 1990 2

Philips Semiconductors Product specification

Phase-locked-loop with lock detector 74HC/HCT7046A

waveforms for the PC1 loop locked at
fo are shown in Fig.7.

The frequency capture range (2fc) is
defined as the frequency range of
input signals on which the PLL will
lock if it was initially out-of-lock. The
frequency lock range (2fL) is defined
as the frequency range of input
signals on which the loop will stay
locked if it was initially in lock. The
capture range is smaller or equal to
the lock range.

With PC1, the capture range depends
on the low-pass filter characteristics
and can be made as large as the lock
range. This configuration retains lock
even with very noisy input signals.
Typical behaviour of this type of
phase comparator is that it can lock to
input frequencies close to the
harmonics of the VCO centre
frequency.

Phase comparator 2 (PC2)

This is a positive edge-triggered
phase and frequency detector. When
the PLL is using this comparator, the
loop is controlled by positive signal
transitions and the duty factors of
SIGIN and COMPIN are not important.
PC2 comprises two D-type flip-flops,
control-gating and a 3-state output
stage. The circuit functions as an
up-down counter (Fig.5) where SIG
causes an up-count and COMPIN a
down-count. The transfer function of
PC2, assuming ripple (f

r=fi

) is
suppressed,
is:

V

CC

V

DEMOUT

where V

DEMOUT

φ

---------- ­4π

–()=

SIGINφCOMPIN

is the demodulator
output at pin 10;
V

DEMOUT=VPC2OUT

(via low-pass

filter).

The phase comparator gain is:

V

K

V

DEMOUT

CC

Vr⁄().=

---------- -

p

4π

is the resultant of the initial
phase differences of SIG
COMP

as shown in Fig.8. Typical

IN

waveforms for the PC2 loop locked at

are shown in Fig.9.

f

o

When the frequencies of SIG
COMP
SIG

are equal but the phase of

IN

leads that of COMPIN, the

IN

p-type output driver at PC2
“ON” for a time corresponding to the
phase difference (φ
the phase of SIG
COMP

, the n-type driver is held

IN

DEMOUT

lags that of

IN

“ON”.
When the frequency of SIG

than that of COMPIN, the p-type
output driver is held “ON” for most of
the input signal cycle time, and for
the remainder of the cycle both n and
p- type drivers are “OFF” (3-state). If
the SIGINfrequency is lower than the
COMPIN frequency, then it is the
n-type driver that is held “ON” for
most of the cycle. Subsequently, the
voltage at the capacitor (C2) of the
low-pass filter connected to PC2
varies until the signal and comparator

IN

inputs are equal in both phase and
frequency. At this stable point the
voltage on C2 remains constant as
the PC2 output is in 3-state and the
VCO input at pin 9 is a high
impedance.

Thus, for PC2, no phase difference
exists between SIGIN and COMP
over the full frequency range of the
VCO. Moreover, the power
dissipation due to the low-pass filter is
reduced because both p and n-type
drivers are “OFF” for most of the
signal input cycle. It should be noted
that the PLL lock range for this type of
phase comparator is equal to the
capture range and is independent of

and

IN

IN

OUT

). When

is higher

IN

and

is held

OUT

IN

the low-pass filter. With no signal
present at SIG

the VCO adjusts, via

IN

PC2, to its lowest frequency.

APPLICATIONS

• FM modulation and demodulation

• Frequency synthesis and

multiplication

• Frequency discrimination

• Tone decoding

• Data synchronization and

conditioning

• Voltage-to-frequency conversion

• Motor-speed control

December 1990 3

Philips Semiconductors Product specification

Phase-locked-loop with lock detector 74HC/HCT7046A

QUICK REFERENCE DATA

GND = 0 V; T

amb

=25°C;

SYMBOL PARAMETER CONDITIONS

f

o

C

I

C

PD

VCO centre frequency C1 = 40 pF; R1 = 3 kΩ; VCC= 5 V 19 19 MHz
input capacitance (pin 5) 3.5 3.5 pF
power dissipation capacitance per package notes 1 and 2 24 24 pF

Notes

1. Applies to the phase comparator section only (VCO disabled).
For power dissipation of VCO and demodulator sections see Figs 20, 21 and 22.

2. C

is used to determine the dynamic power dissipation (PD in µW):

PD

PD=CPD× V

2

× fi+∑(CL× V

CC

2

× fo) where:

CC

fi= input frequency in MHz
fo= output frequency in MHz
∑ (CL× V

2

× fo) = sum of outputs

CC

CL= output load capacitance in pF
VCC= supply voltage in V

ORDERING INFORMATION

“74HC/HCT/HCU/HCMOS Logic Package Information”

See

.

TYPICAL

UNIT

HC HCT

December 1990 4

Philips Semiconductors Product specification

Phase-locked-loop with lock detector 74HC/HCT7046A

PIN DESCRIPTION

PIN NO. SYMBOL NAME AND FUNCTION

1 LD lock detector output (active HIGH)
2 PC1
3 COMP
4 VCO

OUT

IN

OUT

5 INH inhibit input
6C1
7C1

A
B

8 GND ground (0 V)
9 VCO
10 DEM
11 R
12 R
13 PC2
14 SIG
15 C
16 V

IN

OUT
1
2

OUT

IN

LD

CC

phase comparator 1 output
comparator input
VCO output

capacitor C1 connection A
capacitor C1 connection B

VCO input
demodulator output
resistor R1 connection
resistor R2 connection
phase comparator 2 output
signal input
lock detector capacitor input
positive supply voltage

Fig.1 Pin configuration. Fig.2 Logic symbol. Fig.3 IEC logic symbol.

December 1990 5

Philips Semiconductors Product specification

Phase-locked-loop with lock detector 74HC/HCT7046A

13

OUT

PC2

7046A

PHASE

COMPARATOR

identical to 4046A

2

1
LD

MGA847

2

LOCK

DETECTOR

15

LD

C

CLD

C

(b)

R4

R3

1

C2

C1

IN

SIG

314476

IN

COMP

CO OUT

V

B

C1

A

C1

4046A

2

R
12

OUT

PC1

1

PHASE

COMPARATOR

VCO

R2

OUT 13

OUT

PC2

PCP

2

PHASE

COMPARATOR

1

R
11

R1

OUT 15

PC3

3

PHASE

COMPARATOR

IN

VCO

OUTINH

DEM

S

R

5109

Fig.4 Functional diagram.

(a)

December 1990 6

Philips Semiconductors Product specification

Phase-locked-loop with lock detector 74HC/HCT7046A

Fig.6 Phase comparator 1: average output

voltage versus input phase difference:

V

V

DEMOUT

φ

DEMOUT

V

PC1OUT

φ

–=

SIGINφCOMPIN

CC

φ

---------- -

SIGINφCOMPIN

π

–()==

Fig.5 Logic diagram.

Fig.7 Typical waveforms for PLL using phase

comparator 1, loop locked at fo.

December 1990 7

Philips Semiconductors Product specification

Phase-locked-loop with lock detector 74HC/HCT7046A

Fig.8 Phase comparator 2: average output

voltage versus input phase difference:

V

V

DEMOUT

φ

DEMOUT

V

PC2OUT

φ

SIGINφCOMPIN

CC

=

---------- ­4π

˙

–()

–()=

φ

SIGINφCOMPIN

.=

Fig.9 Typical waveforms for PLL using phase

comparator 2, loop locked at f

o.

December 1990 8

Philips Semiconductors Product specification

Phase-locked-loop with lock detector 74HC/HCT7046A

RECOMMENDED OPERATING CONDITIONS FOR 74HC/HCT

SYMBOL PARAMETER

74HC 74HCT

min. typ. max. min. typ. max.

V
V

V
V
T
T

tr, t

CC
CC

I
O
amb
amb

f

DC supply voltage 3.0 5.0 6.0 4.5 5.0 5.5 V
DC supply voltage if VCO section is

not used
DC input voltage range 0 V
DC output voltage range 0 V

2.0 5.0 6.0 4.5 5.0 5.5 V
0V

CC

0V

CC

operating ambient temperature range −40 +85 −40 +85 °C see DC and AC
operating ambient temperature range −40 +125 −40 +125 °C

input rise and fall times (pin 5)

6.0

1000
500

6.0 500 ns

400

RATINGS

Limiting values in accordance with the Absolute Maximum System (IEC 134)
Voltages are referenced to GND (ground = 0 V)

SYMBOL PARAMETER MIN. MAX. UNIT CONDITIONS

V

CC

±I

IK

±I

OK

±I

O

±I

;

CC

±I

GND

T

stg

P

tot

DC supply voltage −0.5 +7V
DC input diode current 20 mA for VI<−0.5 V or VI> VCC+ 0.5 V
DC output diode current 20 mA for VO<−0.5 V or VO> VCC+ 0.5 V
DC output source or sink current 25 mA for − 0.5 V < VO< VCC+ 0.5 V
DC VCC or GND current

50 mA

storage temperature range −65 +150 °C
power dissipation per package

for temperature range: −40 to +125 °C
74HC/HCT

plastic DIL 750 mW

above +70 °C: derate linearly with 12 mW/K

plastic mini-pack (SO) 500 mW above +70 °C: derate linearly with 8 mW/K

UNIT CONDITIONS

V

CC

V

CC

CHARACTER­ISTICS

VCC= 2.0 V
VCC= 4.5 V
VCC= 6.0 V

December 1990 9

Philips Semiconductors Product specification

Phase-locked-loop with lock detector 74HC/HCT7046A

DC CHARACTERISTICS FOR 74HC
Quiescent supply current

Voltages are referenced to GND (ground = 0 V)

SYMBOL PARAMETER

I

CC

quiescent supply
current

(VCO disabled)

(°C)

T

amb

74HC

min. typ. max. min. max. min. max.

8.0 80.0 160.0 µA 6.0 pins 3, 5, and 14 at

UNIT

TEST CONDITIONS

V

CC

(V)

OTHER+25 −40 to +85 −40 to +125

VCC; pin 9 at GND;
II at pins 3 and 14
to be excluded

December 1990 10

Philips Semiconductors Product specification

Phase-locked-loop with lock detector 74HC/HCT7046A

Phase comparator section

Voltages are referenced to GND (ground = 0 V)

SYMBOL PARAMETER

DC coupled HIGH

V

IH

level input voltage

SIGIN, COMP

IN

DC coupled LOW level

V

V

V

IL

OH

OH

input voltage

SIGIN, COMP

HIGH level output

IN

voltage

LD, PC

nOUT

HIGH level output

voltage

LD, PC

nOUT

LOW level output

V

OL

voltage

LD, PC

nOUT

LOW level output

V

±I

±I

OL

I

OZ

voltage

LD, PC

nOUT

input leakage current

SIGIN, COMP

IN

3-state

OFF-state current
PC2

OUT

R

I

input resistance

SIGIN, COMP

IN

(°C)

T

amb

74HC

min. typ. max. min. max. min. max.

1.5

3.15

4.2

1.9

4.4

5.9

3.98

5.48

1.2

2.4

3.2

0.8

2.1

2.8

2.0

4.5

6.0

4.32

5.81
0

0
0

0.15

0.16

0.5

1.35

1.8

0.1

0.1

0.1

0.26

0.26

3.0

7.0

18.0

30.0

1.5

3.15

4.2

1.9

4.4

5.9

3.84

5.34

0.5

1.35

1.8

0.1

0.1

0.1

0.33

0.33

4.0

9.0

23.0

38.0

1.5

3.15

4.2

0.5

1.35

1.8

1.9

4.4

5.9

3.7

5.2

0.1

0.1

0.1

0.4

0.4

5.0

11.0

27.0

45.0

0.5 5.0 10.0 µA 6.0 V

800
250
150

UNIT

V

(V)

2.0

V

4.5

6.0

2.0

V

4.5

6.0

2.0

V

4.5

6.0

V

4.5

6.0

2.0

V

4.5

6.0

V

4.5

6.0

µA 2.0

3.0

4.5

6.0

kΩ 3.0

4.5

6.0

TEST CONDITIONS

V

CC

V
or
V

V
or
V

V
or
V

V
or
V

V

I

IH

IL
IH

IL
IH

IL
IH

IL

CC

OTHER+25 −40 to +85 −40 to +125

−IO=20µA

−IO=20µA

−IO=20µA

−IO= 4.0 mA

= 5.2 mA

−I

O

IO=20µA
IO=20µA
IO=20µA

IO= 4.0 mA

= 5.2 mA

I

O

or

GND

VO=V

IH

or
V

IL

VI at self-bias
operating point;

= 0.5 V; see

∆V

I

Figs 10, 11 and 12

CC

or GND

December 1990 11

Philips Semiconductors Product specification

Phase-locked-loop with lock detector 74HC/HCT7046A

VCO section

Voltages are referenced to GND (ground = 0 V)

SYM-

BOL

PARAMETER

HIGH level

V

IH

input voltage
INH

LOW level

V

IL

input voltage
INH

HIGH level

V

V

OH

OH

output voltage
VCO

OUT

HIGH level

output voltage
VCO

OUT

LOW level

V

OL

output voltage
VCO

OUT

LOW level

V

OL

output voltage
VCO

OUT

LOW level output

V

OL

voltage C1A,C1
(test purposes only)

±I

input leakage current

I

INH, VCO

IN

R1 resistor range

R2 resistor range

C1 capacitor range

V

VCOIN

operating voltage

range at VCO

T

amb

(°C)

TEST CONDITIONS

74HC

UNIT

V

CC

(V)

V

I

OTHER+25 −40 to +85 −40 to +125

min. typ. max. min. max. min. max.

2.1

1.7

3.15

2.4

4.2

3.2

1.3

0.9

2.1

1.35

2.8

1.8

2.9

3.0

4.4

4.5

5.9

6.0

3.98

4.32

5.48

5.81
0

0.1

0

0.1

0

0.1

0.15

0.26

0.16

0.26

B

0.40

0.40

0.1 1.0 1.0 µA 6.0

3.0

3.0

3.0

3.0

3.0

3.0
40

40
40

1.1

IN

1.1

1.1

300
300
300

300
300
300

no
limit

1.9

3.4

4.9

2.1

3.15

4.2

2.9

4.4

5.9

3.84

5.34

0.9

1.35

1.8

0.1

0.1

0.1

0.33

0.33

0.47

0.47

2.1

3.15

4.2

2.9

4.4

5.9

3.7

5.2

0.9

1.35

1.8

0.1

0.1

0.1

0.4

0.4

0.54

0.54

V

V

V

V

V

V

V

kΩ

kΩ

pF

V

3.0

4.5

6.0

3.0

4.5

6.0

3.0

4.5

6.0

4.5

6.0

3.0

4.5

6.0

4.5

6.0

4.5

6.0

3.0

4.5

6.0

3.0

4.5

6.0

3.0

4.5

6.0

3.0

4.5

6.0

V

−IO=20µA

IH

or

−IO=20µA

V

−IO=20µA

IL

V

IH

−IO= 4.0 mA

or

−IO= 5.2 mA

V

IL

V

IO=20µA

IH

or

IO=20µA

V

IO=20µA

IL

V

IH

IO= 4.0 mA

or

IO= 5.2 mA

V

IL

V

IH

IO= 4.0 mA

or

IO= 5.2 mA

V

IL

V

CC

or

GND

note 1

note 1

over the range
specified for R1;
for linearity see
Figs 18 and 19.

Note

1. The parallel value of R1 and R2 should be more than 2.7 kΩ. Optimum performance is achieved when R1 and/or R2
are/is > 10 kΩ.

December 1990 12