Philips 74hc hct646 DATASHEETS

INTEGRATED CIRCUITS

DATA SH EET

For a complete data sheet, please also download:

•The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications

•The IC06 74HC/HCT/HCU/HCMOS Logic Package Information

•The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines

74HC/HCT646

Octal bus transceiver/register;
3-state

Product specification
File under Integrated Circuits, IC06

September 1993

Philips Semiconductors Product specification

Octal bus transceiver/register; 3-state 74HC/HCT646

FEATURES

• Independent register for A and B buses

• Multiplexed real-time and stored data

• Output capability: bus driver

• ICC category: MSI

clocked into the registers as the appropriate clock

and CPBA) goes to a HIGH logic level. Output

(CP

AB

enable (OE) and direction (DIR) inputs are provided to
control the transceiver function. In the transceiver mode,
data present at the high-impedance port may be stored in
either the “A” or “B” register, or in both. The select source
inputs (SABand SBA) can multiplex stored and real-time
(transparent mode) data. The direction (DIR) input

GENERAL DESCRIPTION

The 74HC/HCT646 are high-speed Si-gate CMOS devices
and are pin compatible with low power Schottky TTL
(LSTTL). They are specified in compliance with JEDEC
standard no. 7A.

The 74HC/HCT646 consist of bus transceiver circuits with
3-state outputs, D-type flip-flops, and control circuitry
arranged for multiplexed transmission of data directly from
the internal registers. Data on the “A” or “B” bus will be

determines which bus will receive data when OE is active
(LOW). In the isolation mode (OE = HIGH), “A” data may
be stored in the “B” register and/or “B” data may be stored
in the “A” register.
When an output function is disabled, the input function is
still enabled and may be used to store and transmit data.
Only one of the two buses, A or B, may be driven at a time.

The “646” is functionally identical to the “648”, but has
non-inverting data paths.

QUICK REFERENCE DATA

GND = 0 V; T

=25°C; tr=tf= 6 ns

amb

SYMBOL PARAMETER CONDITIONS

t

PHL

f

max

C
C

I
PD

/ t

PLH

propagation delay An, Bn to Bn, A

n

CL= 15 pF; VCC=5V 11 13 ns
maximum clock frequency 69 85 MHz
input capacitance 3.5 3.5 pF
power dissipation capacitance per channel notes 1 and 2 30 33 pF

TYPICAL

UNIT

HC HCT

Notes

1. C

is used to determine the dynamic power dissipation (PD in µW):

PD

PD=CPD× V

2

× fi+ ∑ (CL× V

CC

2

× fo) where:

CC

fi= input frequency in MHz
fo= output frequency in MHz
∑ (CL× V

2

× fo) = sum of outputs

CC

CL= output load capacitance in pF
VCC= supply voltage in V

2. For HC the condition is VI= GND to V

CC

For HCT the condition is VI= GND to VCC− 1.5 V

ORDERING INFORMATION

“74HC/HCT/HCU/HCMOS Logic Package Information”

See

September 1993 2

.

Philips Semiconductors Product specification

Octal bus transceiver/register; 3-state 74HC/HCT646

PIN DESCRIPTION

PIN NO. SYMBOL NAME AND FUNCTION

1CP
2S

AB

AB

3 DIR direction control input
4, 5, 6, 7, 8, 9, 10, 11 A

to A

0

7

12 GND ground (0 V)
20, 19, 18, 17, 16, 15, 14, 13 B
21
22 S
23 CP
24 V

to B

0

7

OE output enable input (active LOW)

BA

BA

CC

A to B clock input (LOW-to-HIGH, edge-triggered)
select A to B source input

A data inputs/outputs

B data inputs/outputs

select B to A source input
B to A clock input (LOW-to-HIGH, edge-triggered)
positive supply voltage

Fig.1 Pin configuration. Fig.2 Logic symbol. Fig.3 IEC logic symbol.

September 1993 3

Philips Semiconductors Product specification

Octal bus transceiver/register; 3-state 74HC/HCT646

Fig.4 Functional diagram.

FUNCTION TABLE

INPUTS

(1)

DATA I/O

(2)

FUNCTION

OE DIR CP

H
H

L
L

L
L

X
X

L
L

H
H

H or L↑H or L↑X

X
X

X
H or LXX

AB

CP

BA

X
H or LXX

S

AB

X

L
H

S

BA

X
X

L
H

X
X

A0to A

B0to B

7

input input

output input

input output

7

isolation
store A and B data

real-time B data to A bus
stored B data to A bus

real-time A data to B bus
stored A data to B bus

Notes

1. H = HIGH voltage level
L = LOW voltage level
X = don’t care
↑ = LOW-to-HIGH level transition

2. The data output functions may be enabled or disabled by various signals at the

OE and DIR inputs. Data input
functions are always enabled, i.e., data at the bus inputs will be stored on every LOW-to-HIGH transition on the clock
inputs.

September 1993 4