Philips 74hc hct597 DATASHEETS

INTEGRATED CIRCUITS

DATA SH EET

For a complete data sheet, please also download:

•The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications

•The IC06 74HC/HCT/HCU/HCMOS Logic Package Information

•The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines

74HC/HCT597

8-bit shift register with input
flip-flops

Product specification
File under Integrated Circuits, IC06

December 1990

Philips Semiconductors Product specification

8-bit shift register with input flip-flops 74HC/HCT597

FEATURES

• 8-bit parallel storage register inputs

• Shift register has direct overriding load and clear

• Output capability: standard

• ICC category: MSI

GENERAL DESCRIPTION

The 74HC/HCT597 are high-speed Si-gate CMOS devices
and are pin compatible with low power Schottky TTL
(LSTTL). They are specified in compliance with JEDEC
standard no. 7A.

The 74HC/HCT597 consist each of an 8-bit storage
register feeding a parallel-in, serial-out 8-bit shift register.
Both the storage register and the shift register have
positive edge-triggered clocks. The shift register also has
direct load (from storage) and clear inputs.

QUICK REFERENCE DATA

GND = 0 V; T

=25°C; tr=tf= 6 ns

amb

SYMBOL PARAMETER CONDITIONS

t

PHL

/ t

PLH

propagation delay CL= 15 pF; VCC=5V

SH

to Q 17 20 ns

CP

ST

to Q 25 29 ns

CP

PL to Q 21 26 ns

f

max

C
C

I
PD

maximum clock frequency SH

CP

input capacitance 3.5 3.5 pF
power dissipation capacitance per package notes 1 and 2 29 32 pF

TYPICAL

UNIT

HC HCT

96 83 MHz

Notes

1. C

is used to determine the dynamic power dissipation (PD in µW):

PD

PD=CPD× V

2

× fi+ ∑ (CL× V

CC

2

× fo) where:

CC

fi= input frequency in MHz
fo= output frequency in MHz
∑ (CL× V

2

× fo) = sum of outputs

CC

CL= output load capacitance in pF
VCC= supply voltage in V

2. For HC the condition is VI= GND to V

CC

For HCT the condition is VI= GND to VCC− 1.5 V

ORDERING INFORMATION

See

“74HC/HCT/HCU/HCMOS Logic Package Information”

.

December 1990 2

Philips Semiconductors Product specification

8-bit shift register with input flip-flops 74HC/HCT597

PIN DESCRIPTION

PIN NO. SYMBOL NAME AND FUNCTION

8 GND ground (0 V)
9 Q serial data output
10
11 SH
12 ST
13
14 D
15, 1, 2, 3, 4, 5, 6, 7 D
16 V

MR asynchronous reset input (active LOW)

CP

CP

shift clock input (LOW-to-HIGH, edge-triggered)
storage clock input (LOW-to-HIGH, edge-triggered)

PL parallel load input (active LOW)

S

to D

0

CC

7

serial data input
parallel data inputs
positive supply voltage

Fig.1 Pin configuration. Fig.2 Logic symbol. Fig.3 IEC logic symbol.

December 1990 3

Philips Semiconductors Product specification

8-bit shift register with input flip-flops 74HC/HCT597

Fig.4 Functional diagram.

FUNCTION TABLE

ST

CP

SH

PL MR FUNCTION

CP

↑ X X X data loaded to input latches
↑ X L H data loaded from inputs to shift register

no clock edge X L H data transferred from input flip-flops to shift register
X X L L invalid logic, state of shift register indeterminate when signals removed
X X H L shift register cleared
X ↑ H H shift register clocked Q

n=Qn−1

, Q0=D

S

Notes

1. H = HIGH voltage level
L = LOW voltage level
X = don’t care
↑ = LOW-to-HIGH CP transition

December 1990 4