Philips 74hc hct540 DATASHEETS

INTEGRATED CIRCUITS

DATA SH EET

For a complete data sheet, please also download:

•The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications

•The IC06 74HC/HCT/HCU/HCMOS Logic Package Information

•The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines

74HC/HCT540

Octal buffer/line driver; 3-state;
inverting

Product specification
File under Integrated Circuits, IC06

December 1990

Philips Semiconductors Product specification

Octal buffer/line driver; 3-state;
inverting

FEATURES

• Inverting outputs

• Output capability: bus driver

• ICC category: MSI

GENERAL DESCRIPTION

The 74HC/HCT540 are high-speed Si-gate CMOS devices
and are pin compatible with low power Schottky TTL
(LSTTL). They are specified in compliance with JEDEC
standard no. 7A.

QUICK REFERENCE DATA

GND = 0 V; T

= 25 °C; tr= tf= 6 ns

amb

SYMBOL PARAMETER CONDITIONS

t

PHL

C
C

I
PD

/ t

PLH

propagation delay Anto Y

n

input capacitance 3.5 3.5 pF
power dissipation capacitance per buffer notes 1 and 2 39 44 pF

The 74HC/HCT540 are octal inverting buffer/line drivers
with 3-state outputs. The 3-state outputs are controlled by
the output enable inputs
A HIGH on OEncauses the outputs to assume a high
impedance OFF-state.
The “540” is identical to the “541” but has inverting outputs.

CL= 15 pF; VCC= 5 V 9 11 ns

74HC/HCT540

OE1and OE2.

TYPICAL

UNIT

HC HCT

Notes

1. C

is used to determine the dynamic power dissipation (PDin µW):

PD

PD= CPD× V

2

× fi+∑(CL× V

CC

2

× fo) where:

CC

fi= input frequency in MHz
fo= output frequency in MHz
∑ (CL× V

2

× fo) = sum of outputs

CC

CL= output load capacitance in pF
VCC= supply voltage in V

2. For HC the condition is VI= GND to V

CC

For HCT the condition is VI= GND to VCC− 1.5 V

ORDERING INFORMATION

“74HC/HCT/HCU/HCMOS Logic Package Information”

See

.

December 1990 2

Philips Semiconductors Product specification

Octal buffer/line driver; 3-state; inverting 74HC/HCT540

PIN DESCRIPTION

PIN NO. SYMBOL NAME AND FUNCTION

1, 19
2, 3, 4, 5, 6, 7, 8, 9 A
10 GND ground (0 V)
18, 17, 16, 15, 14, 13, 12, 11
20 V

OE1, OE

to A

0

Y0to Y

CC

2

7

7

output enable input (active LOW)
data inputs

bus outputs
positive supply voltage

Fig.1 Pin configuration. Fig.2 Logic symbol. Fig.3 IEC logic symbol.

December 1990 3