Philips 74hc hct534 DATASHEETS

INTEGRATED CIRCUITS

DATA SH EET

For a complete data sheet, please also download:

•The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications

•The IC06 74HC/HCT/HCU/HCMOS Logic Package Information

•The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines

74HC/HCT534

Octal D-type flip-flop; positive
edge-trigger; 3-state; inverting

Product specification
Supersedes data of September 1993
File under Integrated Circuits, IC06

1998 Apr 10

Philips Semiconductors Product specification

Octal D-type flip-flop; positive edge-trigger;
3-state; inverting

FEATURES

• 3-state inverting outputs for bus oriented applications

• 8-bit positive, edge-triggered register

• Common 3-state output enable input

• Output capability: bus driver

• ICC category: MSI.

GENERAL DESCRIPTION

The 74HC/HCT534 are high-speed Si-gate CMOS devices
and are pin compatible with low power Schottky TTL
(LSTTL). They are specified in compliance with JEDEC
standard no. 7A.

QUICK REFERENCE DATA

GND = 0 V; T

=25°C; tr=tf=6ns

amb

SYMBOL PARAMETER CONDITIONS

t

PHL

f

max

C
C

I
PD

/ t

PLH

propagation delay CP to Q

n

maximum clock frequency 61 40 MHz
input capacitance 3.5 3.5 pF
power dissipation capacitance per flip-flop notes 1 and 2 19 19 pF

The 74HC/HCT534 are octal D-type flip-flops featuring
separate D-type inputs for each flip-flop and inverting
3-state outputs for bus oriented applications. A clock (CP)
and an output enable (
flip-flops.

The 8 flip-flops will store the state of their individual
D-inputs that meet the set-up and hold times requirements
on the LOW-to-HIGH CP transition. When OE is LOW, the
contents of the 8 flip-flops are available at the outputs.
When OE is HIGH, the outputs go to the high impedance
OFF-state. Operation of the OE input does not affect the
state of the flip-flops.

The “534” is functionally identical to the “374”, but has
inverted outputs.

CL= 15 pF; VCC=5V 12 13 ns

74HC/HCT534

OE) input are common to all

TYPICAL

UNIT

HC HCT

Notes

1. C

is used to determine the dynamic power dissipation (PDin µW):

PD

PD=CPD× V

2

× fi+∑(CL× V

CC

2

× fo) where:

CC

fi= input frequency in MHz.
fo= output frequency in MHz.
∑ (CL× V

2

× fo) = sum of outputs.

CC

CL= output load capacitance in pF.
VCC= supply voltage in V.

2. For HC the condition is VI= GND to VCC; for HCT the condition is VI= GND to VCC− 1.5 V.

ORDERING INFORMATION

TYPE

NUMBER

NAME DESCRIPTION VERSION

PACKAGE

74HC534 SO20 plastic small outline package; 20 leads; body width 7.5 mm SOT163-1
74HC534 DIP20 plastic dual in-line package; 20 leads (300 mil) SOT146-1
74HCT534 SO20 plastic small outline package; 20 leads; body width 7.5 mm SOT163-1
74HCT534 DIP20 plastic dual in-line package; 20 leads (300 mil) SOT146-1

1998 Apr 10 2

Philips Semiconductors Product specification

Octal D-type flip-flop; positive edge-trigger;
3-state; inverting

PIN DESCRIPTION

PIN NO. SYMBOL NAME AND FUNCTION

1
2, 5, 6, 9, 12, 15, 16, 19
3, 4, 7, 8, 13, 14, 17, 18 D
10 GND ground (0 V)
11 CP clock input (LOW-to-HIGH, edge-triggered)
20 V

page

OE

1
2

Q

0

D

3

0

D

4

1

5

Q
Q
D
D

Q

GND

1
2
2
3

3

534

6
7
8
9

10

MGM954

OE 3-state output enable input (active LOW)

20
19
18
17
16
15
14
13
12
11

Q0to Q

0

CC

V

CC

Q

7

D

7

D

6

Q

6

Q

5

D

5

D

4

Q

4

CP

to D

7

7

3-state outputs
data inputs

positive supply voltage

age

3

D

4

D

7

D

8

D

13

D

14

D

17

D

18

D

11

CP
0
1
2
3
4
5
6
7

OE

1

Q
Q
Q
Q
Q
Q
Q
Q

0
1
2
3
4
5
6
7

MGM955

2
5
6

9
12
15
16
19

page

74HC/HCT534

1

EN

11

C1

3

1D

4
7

8
13
14
17
18

MGM956

2
5
6

9
12
15
16
19

Fig.1 Pin configuration.

Fig.2 Logic symbol.

1998 Apr 10 3

Fig.3 IEC logic symbol.

Philips Semiconductors Product specification

Octal D-type flip-flop; positive edge-trigger;
3-state; inverting

handbook, halfpage

D

3

0

D

1

4

D

7

2

D
D
D
D
D

CP
OE

FF1

3

to

4

FF8

5
6
7

3-STATE

OUTPUTS

8
13
14
17
18

11

1

Q

0

Q

1

Q

2

Q

3

Q

4

Q

5

Q

6

Q

7

MGM957

74HC/HCT534

2
5
6

9
12
15
16
19

Fig.4 Functional diagram.

FUNCTION TABLE

OPERATING MODES

INPUTS

OE CP D

INTERNAL FLIP-FLOPS

n

OUTPUTS

Q0to Q

7

load and read register L ↑ lL H

L↑hH L

load register and disable outputs H ↑ lL Z

H↑hH Z

Note

1. H = HIGH voltage level; h = HIGH voltage level one set-up time prior to the LOW-to-HIGH CP transition
L = LOW voltage level; I = LOW voltage level one set-up time prior to the LOW-to-HIGH CP transition
Z = high impedance OFF-state; ↑ = LOW-to-HIGH clock transition.

1998 Apr 10 4