Philips 74hc hct4518 DATASHEETS

INTEGRATED CIRCUITS

DATA SH EET

For a complete data sheet, please also download:

•The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications

•The IC06 74HC/HCT/HCU/HCMOS Logic Package Information

•The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines

74HC/HCT4518

Dual synchronous BCD counter

Product specification
File under Integrated Circuits, IC06

December 1990

Philips Semiconductors Product specification

Dual synchronous BCD counter 74HC/HCT4518

FEATURES

• Output capability: standard

• ICC category: MSI

all four bit positions (nQ0 to nQ3) and an active HIGH
overriding asynchronous master reset input (nMR).

The counter advances on either the LOW-to-HIGH
transition of nCP0 if nCP1 is HIGH or the HIGH-to-LOW
transition of nCP1 if nCP0 is LOW. Either nCP0 or nCP

GENERAL DESCRIPTION

The 74HC/HCT4518 are high-speed Si-gate CMOS
devices and are pin compatible with the “4518” of the
“4000B” series. They are specified in compliance with

may be used as the clock input to the counter and the other
clock input may be used as a clock enable input. A HIGH
on nMR resets the counter (nQ0 to nQ3= LOW)
independent of nCP0 and nCP1.

JEDEC standard no. 7A.
The 74HC/HCT4518 are dual 4-bit internally synchronous

BCD counters with an active HIGH clock input (nCP

) and

0

an active LOW clock input (nCP1), buffered outputs from

APPLICATIONS

• Multistage synchronous counting

• Multistage asynchronous counting

• Frequency dividers

QUICK REFERENCE DATA

GND = 0 V; T

=25°C; tr=tf= 6 ns

amb

SYMBOL PARAMETER CONDITIONS

t

PHL

t

PHL

f

max

C
C

/ t

I
PD

propagation delay nCP0, nCP1to nQ

PLH

propagation delay nMR to nQ

n

n

CL= 15 pF; VCC=5 V 20 24 ns

maximum clock frequency 61 55 MHz
input capacitance 3.5 3.5 pF
power dissipation capacitance per counter notes 1 and 2 29 27 pF

1

TYPICAL

UNIT

HC HCT

13 14 ns

Notes

1. C

is used to determine the dynamic power dissipation (PD in µW):

PD

PD=CPD× V

2

× fi+∑(CL× V

CC

2

× fo) where:

CC

fi= input frequency in MHz
fo= output frequency in MHz
∑ (CL× V

2

× fo) = sum of outputs

CC

CL= output load capacitance in pF
VCC= supply voltage in V

2. For HC the condition is VI= GND to V

CC

For HCT the condition is VI= GND to VCC− 1.5 V

ORDERING INFORMATION

See

“74HC/HCT/HCU/HCMOS Logic Package Information”

.

December 1990 2

Philips Semiconductors Product specification

Dual synchronous BCD counter 74HC/HCT4518

PIN DESCRIPTION

PIN NO. SYMBOL NAME AND FUNCTION

1, 9 1CP
2, 10 1
3, 4, 5, 6 1Q
7, 15 1MR, 2MR asynchronous master reset inputs (active HIGH)
8 GND ground (0 V)
11, 12, 13, 14 2Q
16 V

, 2CP

0

CP1, 2CP

to 1Q

0

to 2Q

0

CC

clock inputs (LOW-to-HIGH, edge-triggered)

0

clock inputs (HIGH-to-LOW, edge-triggered)

1

3

3

data outputs

data outputs
positive supply voltage

Fig.1 Pin configuration. Fig.2 Logic symbol. Fig.3 IEC logic symbol.

December 1990 3