Philips 74hc hct4515 DATASHEETS

INTEGRATED CIRCUITS

DATA SH EET

For a complete data sheet, please also download:

•The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications

•The IC06 74HC/HCT/HCU/HCMOS Logic Package Information

•The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines

74HC/HCT4515

4-to-16 line decoder/demultiplexer
with input latches; inverting

Product specification
File under Integrated Circuits, IC06

September 1993

Philips Semiconductors Product specification

4-to-16 line decoder/demultiplexer with
input latches; inverting

FEATURES

• Inverting outputs

• Output capability: standard

• ICC category: MSI

GENERAL DESCRIPTION

The 74HC/HCT4515 are high-speed Si-gate CMOS
devices and are pin compatible with “4515” of the “4000B”
series. They are specified in compliance with JEDEC
standard no. 7A.

QUICK REFERENCE DATA

GND = 0 V; T

=25°C; tr=tf= 6 ns

amb

SYMBOL PARAMETER CONDITIONS

t

PHL

C
C

I
PD

/ t

PLH

propagation delay An to Q

n

input capacitance 3.5 3.5 pF
power dissipation capacitance per package notes 1 and 2 44 46 pF

The 74HC/HCT4515 are 4-to-16 line
decoders/demultiplexers having four binary weighted
address inputs (A
(LE), and an active LOW enable input (E). The 16 inverting
outputs (Q0to Q15) are mutually exclusive active LOW.
When LE is HIGH, the selected output is determined by the
data on An. When LE goes LOW, the last data present at
Anare stored in the latches and the outputs remain stable.
When E is LOW, the selected output, determined by the
contents of the latch, is LOW. When E is HIGH, all outputs
are HIGH. The enable input (E) does not affect the state of
the latch.

When the “4515” is used as a demultiplexer, E is the data
input and A0to A3are the address inputs.

CL= 15 pF; VCC=5 V 25 26 ns

74HC/HCT4515

to A3) with latches, a latch enable input

0

TYPICAL

HC HCT

UNIT

Notes

1. C

is used to determine the dynamic power dissipation (PD in µW):

PD

PD=CPD× V

2

× fi+∑ (CL× V

CC

2

× fo) where:

CC

fi= input frequency in MHz
fo= output frequency in MHz
∑ (CL× V

2

× fo) = sum of outputs

CC

CL= output load capacitance in pF
VCC= supply voltage in V

2. For HC the condition is VI= GND to V

CC

For HCT the condition is VI= GND to VCC− 1.5 V

ORDERING INFORMATION

“74HC/HCT/HCU/HCMOS Logic Package Information”

See

.

September 1993 2

Philips Semiconductors Product specification

4-to-16 line decoder/demultiplexer with

74HC/HCT4515

input latches; inverting

PIN DESCRIPTION

PIN NO. SYMBOL NAME AND FUNCTION

1 LE latch enable input (active HIGH)
2, 3, 21, 22 A
11, 9, 10, 8, 7, 6, 5, 4,18, 17, 20, 19, 14, 13, 16, 15
12 GND ground (0 V)
23
24 V

to A

0

3

Q0 to Q

E enable input (active LOW)

15

CC

address inputs
multiplexer outputs (active LOW)

positive supply voltage

Fig.1 Pin configuration. Fig.2 Logic symbol. Fig.3 IEC logic symbol.

September 1993 3