Philips 74hc hct4510 DATASHEETS

INTEGRATED CIRCUITS

DATA SH EET

For a complete data sheet, please also download:

•The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications

•The IC06 74HC/HCT/HCU/HCMOS Logic Package Information

•The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines

74HC/HCT4510

BCD up/down counter

Product specification
File under Integrated Circuits, IC06

December 1990

Philips Semiconductors Product specification

BCD up/down counter 74HC/HCT4510

FEATURES

• Output capability: standard

• ICC category: MSI

parallel load input (PL), four parallel inputs (D0 to D3), four
parallel outputs (Q0 to Q3), an active LOW terminal count
output (TC), and an overriding asynchronous master reset
input (MR).

Information on D0 to D3 is loaded into the counter while PL

GENERAL DESCRIPTION

The 74HC/HCT4510 are high-speed Si-gate CMOS
devices and are pin compatible with the “4510” of the
“4000B” series. They are specified in compliance with
JEDEC standard no. 7A.

The 74HC/HCT4510 are edge-triggered synchronous
up/down BCD counters with a clock input (CP), an
up/down count control input (UP/

DN), an active LOW

is HIGH, independent of all other input conditions except
the MR input, which must be LOW. With PL LOW, the
counter changes on the LOW-to-HIGH transition of CP if
CE is LOW. UP/DN determines the direction of the count,
HIGH for counting up, LOW for counting down. When
counting up,TC is LOW when Q0 and Q3 are HIGH andCE
is LOW. When counting down, TC is LOW when Q0 to Q
and CE are LOW. A HIGH on MR resets the counter (Q0 to
Q3= LOW) independent of all other input conditions.

count enable input (CE), an asynchronous active HIGH

Logic equation for terminal count:

TC = CE . {(UP/DN).Q0.Q3+(UP/DN). Q0.Q1.Q2.Q3}

QUICK REFERENCE DATA

GND = 0 V; T

=25°C; tr=tf= 6 ns

amb

SYMBOL PARAMETER CONDITIONS

t

/ t

PHL

PLH

f

max

C

I

C

PD

propagation delay CP to Q

n

CL= 15 pF; VCC=5 V2123ns
maximum clock frequency 57 58 MHz
input capacitance 3.5 3.5 pF
power dissipation capacitance per package notes 1 and 2 50 53 pF

3

TYPICAL

UNIT

HC HCT

Notes

1. C

is used to determine the dynamic power dissipation (PD in µW):

PD

PD=CPD× V

2

× fi + ∑ (CL× V

CC

2

× fo) where:

CC

fi= input frequency in MHz
fo= output frequency in MHz
∑ (CL× V

2

× fo) = sum of outputs

CC

CL= output load capacitance in pF
VCC= supply voltage in V

2. For HC the condition is VI= GND to VCC. For HCT the condition is VI= GND to VCC− 1.5 V

ORDERING INFORMATION

“74HC/HCT/HCU/HCMOS Logic Package Information”

See

.

December 1990 2

Philips Semiconductors Product specification

BCD up/down counter 74HC/HCT4510

PIN DESCRIPTION

PIN NO. SYMBOL NAME AND FUNCTION

1 PL parallel load input (active HIGH)
4, 12, 13, 3 D
5
6, 11, 14, 2 Q
7
8 GND ground (0 V)
9 MR asynchronous master reset input (active HIGH)
10 UP/
15 CP clock input (LOW-to-HIGH, edge-triggered)
16 V

to D

0

3

parallel inputs

CE count enable input (active LOW)

to Q

0

3

parallel outputs

TC terminal count output (active LOW)

DN up/down control input

CC

positive supply voltage

Fig.1 Pin configuration. Fig.2 Logic symbol. Fig.3 IEC logic symbol.

December 1990 3

Philips Semiconductors Product specification

BCD up/down counter 74HC/HCT4510

FUNCTION TABLE

Fig.4 Functional diagram.

MR PL UP/

L
L
L
L
H

Notes

1. H = HIGH voltage level

H

L
L
L

X

L = LOW voltage level
X = don’t care
↑ = LOW-to-HIGH clock transition

DN CE CP MODE

X
X
L
H
X

X

X

H

X
L
L
X

↑

↑

X

parallel load
no change
count down
count up
reset

Fig.5 Timing diagram.

December 1990 4