Philips 74hc hct4046a DATASHEETS

INTEGRATED CIRCUITS

DATA SH EET

For a complete data sheet, please also download:

•The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications

•The IC06 74HC/HCT/HCU/HCMOS Logic Package Information

•The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines

74HC/HCT4046A

Phase-locked-loop with VCO

Product specification
Supersedes data of September 1993
File under Integrated Circuits, IC06

1997 Nov 25

Philips Semiconductors Product specification

Phase-locked-loop with VCO 74HC/HCT4046A

FEATURES

• Low power consumption

• Centre frequency of up to 17 MHz (typ.) at VCC= 4.5 V

• Choice of three phase comparators: EXCLUSIVE-OR;

edge-triggered JK flip-flop;
edge-triggered RS flip-flop

• Excellent VCO frequency linearity

• VCO-inhibit control for ON/OFF keying and for low

standby power consumption

• Minimal frequency drift

• Operating power supply voltage range:

VCO section 3.0 to 6.0 V
digital section 2.0 to 6.0 V

• Zero voltage offset due to op-amp buffering

• Output capability: standard

category: MSI.

• I

CC

GENERAL DESCRIPTION

The 74HC/HCT4046A are high-speed Si-gate CMOS
devices and are pin compatible with the “4046” of the
“4000B” series. They are specified in compliance with
JEDEC standard no. 7A.

The 74HC/HCT4046A are phase-locked-loop circuits that
comprise a linear voltage-controlled oscillator (VCO) and
three different phase comparators (PC1, PC2 and PC3)
with a common signal input amplifier and a common
comparator input.

The signal input can be directly coupled to large voltage
signals, or indirectly coupled (with a series capacitor) to
small voltage signals. A self-bias input circuit keeps small
voltage signals within the linear region of the input
amplifiers. With a passive low-pass filter, the “4046A”
forms a second-order loop PLL. The excellent VCO
linearity is achieved by the use of linear op-amp
techniques.

The VCO requires one external capacitor C1 (between

and C1B) and one external resistor R1 (between

C1

A

R1and GND) or two external resistors R1 and R2
(between R1and GND, and R2and GND). Resistor R1
and capacitor C1 determine the frequency range of the
VCO. Resistor R2 enables the VCO to have a frequency
offset if required.

The high input impedance of the VCO simplifies the design
of low-pass filters by giving the designer a wide choice of
resistor/capacitor ranges. In order not to load the low-pass
filter, a demodulator output of the VCO input voltage is

provided at pin 10 (DEM
techniques where the DEM

). In contrast to conventional

OUT

voltage is one threshold

OUT

voltage lower than the VCO input voltage, here the
DEM
DEM
from DEM
open. The VCO output (VCO

voltage equals that of the VCO input. If

OUT

is used, a load resistor (RS) should be connected

OUT

to GND; if unused, DEM

OUT

) can be connected

OUT

should be left

OUT

directly to the comparator input (COMPIN), or connected
via a frequency-divider. The VCO output signal has a duty
factor of 50% (maximum expected deviation 1%), if the
VCO input is held at a constant DC level. A LOW level at
the inhibit input (INH) enables the VCO and demodulator,
while a HIGH level turns both off to minimize standby
power consumption.

The only difference between the HC and HCT versions is
the input level specification of the INH input. This input
disables the VCO section. The sections of the comparator
are identical, so that there is no difference in the
SIGIN(pin 14) or COMPIN(pin 3) inputs between the HC
and HCT versions.

Phase comparators

The signal input (SIG

) can be directly coupled to the

IN

self-biasing amplifier at pin 14, provided that the signal
swing is between the standard HC family input logic levels.
Capacitive coupling is required for signals with smaller
swings.

Phase comparator 1 (PC1)

This is an EXCLUSIVE-OR network. The signal and
comparator input frequencies (fi) must have a 50% duty
factor to obtain the maximum locking range. The transfer
characteristic of PC1, assuming ripple (f

V

suppressed, is:

where V
V

DEMOUT

DEMOUT=VPC1OUT

V

DEMOUT

is the demodulator output at pin 10;

(via low-pass filter).

The phase comparator gain is:

CC

---------- -

π

K

p

=2fi) is

r

φ

–()=

SIGINφCOMPIN

V

CC

˙

Vr⁄()

---------- -

π

.=

The average output voltage from PC1, fed to the VCO
input via the low-pass filter and seen at the demodulator
output at pin 10 (V

DEMOUT

differences of signals (SIG
(COMP

equal to
SIG
frequency (f
at f

) as shown in Fig.6. The average of V

IN

1

⁄2VCCwhen there is no signal or noise at

and with this input the VCO oscillates at the centre

IN

). Typical waveforms for the PC1 loop locked

o

are shown in Fig.7.

o

), is the resultant of the phase

) and the comparator input

IN

DEMOUT

is

1997 Nov 25 2

Philips Semiconductors Product specification

Phase-locked-loop with VCO 74HC/HCT4046A

The frequency capture range (2fc) is defined as the
frequency range of input signals on which the PLL will lock
if it was initially out-of-lock. The frequency lock range
(2fL) is defined as the frequency range of input signals on
which the loop will stay locked if it was initially in lock. The
capture range is smaller or equal to the lock range.

With PC1, the capture range depends on the low-pass
filter characteristics and can be made as large as the lock
range.
This configuration retains lock even with very noisy input
signals. Typical behaviour of this type of phase
comparator is that it can lock to input frequencies close to
the harmonics of the VCO centre frequency.

Phase comparator 2 (PC2)

This is a positive edge-triggered phase and frequency
detector. When the PLL is using this comparator, the loop
is controlled by positive signal transitions and the duty
factors of SIGINand COMPINare not important. PC2
comprises two D-type flip-flops, control-gating and a
3-state output stage. The circuit functions as an up-down
counter (Fig.5) where SIG
COMP
assuming ripple (f

is:

where V
V

DEMOUT=VPC2OUT

a down-count. The transfer function of PC2,

IN

r=fi

V

V

DEMOUT

DEMOUT

CC

---------- ­4π

is the demodulator output at pin 10;

(via low-pass filter).

The phase comparator gain is:

V

DEMOUT

is the resultant of the initial phase differences of

causes an up-count and

IN

) is suppressed,

–()=

φ

SIGINφCOMPIN

V

K

---------- -

p

4π

CC

Vr⁄().=

SIGINand COMPINas shown in Fig.8. Typical waveforms
for the PC2 loop locked at foare shown in Fig.9.

When the frequencies of SIGINand COMPINare equal but
the phase of SIGINleads that of COMPIN, the p-type
output driver at PC2
corresponding to the phase difference (φ

is held “ON” for a time

OUT

DEMOUT

). When
the phase of SIGINlags that of COMPIN, the n-type driver
is held “ON”.

When the frequency of SIGINis higher than that of
COMPIN, the p-type output driver is held “ON” for most of
the input signal cycle time, and for the remainder of the
cycle both n and p- type drivers are ”OFF” (3-state). If the
SIGINfrequency is lower than the COMPINfrequency, then
it is the n-type driver that is held “ON” for most of the cycle.
Subsequently, the voltage at the capacitor (C2) of the
low-pass filter connected to PC2

varies until the signal

OUT

and comparator inputs are equal in both phase and
frequency. At this stable point the voltage on C2 remains
constant as the PC2 output is in 3-state and the VCO input
at pin 9 is a high impedance. Also in this condition, the
signal at the phase comparator pulse output (PCP

OUT

) is a
HIGH level and so can be used for indicating a locked
condition.

Thus, for PC2, no phase difference exists between
SIGINand COMPINover the full frequency range of the
VCO. Moreover, the power dissipation due to the low-pass
filter is reduced because both p and n-type drivers are
“OFF” for most of the signal input cycle. It should be noted
that the PLL lock range for this type of phase comparator
is equal to the capture range and is independent of the
low-pass filter. With no signal present at SIGINthe
VCO adjusts, via PC2, to its lowest frequency.

Phase comparator 3 (PC3)

This is a positive edge-triggered sequential phase detector
using an RS-type flip-flop. When the PLL is using this
comparator, the loop is controlled by positive signal
transitions and the duty factors of SIGINand COMPINare
not important. The transfer characteristic of PC3,
assuming ripple (f

is:

V

DEMOUT

where V
V

DEMOUT

DEMOUT=VPC3OUT

The phase comparator gain is:

) is suppressed,

r=fi

V

CC

φ

---------- ­2π

–()=

SIGINφCOMPIN

is the demodulator output at pin 10;

(via low-pass filter).

V

K

CC

Vr⁄().=

---------- -

p

2π

The average output from PC3, fed to the VCO via the
low-pass filter and seen at the demodulator output at
pin 10 (V

DEMOUT

), is the resultant of the phase differences
of SIGINand COMPINas shown in Fig.10. Typical
waveforms for the PC3 loop locked at foare shown in
Fig.11.

The phase-to-output response characteristic of PC3
(Fig.10) differs from that of PC2 in that the phase angle
between SIGINand COMPINvaries between 0° and
360° and is 180° at the centre frequency. Also PC3 gives
a greater voltage swing than PC2 for input phase
differences but as a consequence the ripple content of the
VCO input signal is higher. The PLL lock range for this type
of phase comparator and the capture range are dependent
on the low-pass filter. With no signal present at SIGINthe
VCO adjusts, via PC3, to its lowest frequency.

1997 Nov 25 3

Philips Semiconductors Product specification

Phase-locked-loop with VCO 74HC/HCT4046A

QUICK REFERENCE DATA

GND = 0 V; T

amb

=25°C

SYMBOL PARAMETER CONDITIONS

UNIT

HC HCT

TYPICAL

f

o

C

I

C

PD

VCO centre frequency C1 = 40 pF; R1 = 3 kΩ;VCC= 5 V 19 19 MHz
input capacitance (pin 5) 3.5 3.5 pF
power dissipation capacitance per

notes 1 and 2 24 24 pF

package

Notes

1. C

is used to determine the dynamic power dissipation (PDin µW):

PD

PD=CPD× V

2

× fi+ ∑ (CL× V

CC

2

× fo) where:

CC

fi= input frequency in MHz.
fo= output frequency in MHz.
CL= output load capacitance in pF.
VCC= supply voltage in V.
∑ (CL× V

2

× fo) = sum of outputs.

CC

2. Applies to the phase comparator section only (VCO disabled). For power dissipation of the VCO and demodulator
sections see Figs 22, 23 and 24.

ORDERING INFORMATION

“74HC/HCT/HCU/HCMOS Logic Package Information”

See

.

APPLICATIONS

• FM modulation and demodulation

• Frequency synthesis and multiplication

• Frequency discrimination

• Tone decoding

• Data synchronization and conditioning

• Voltage-to-frequency conversion

• Motor-speed control.

PACKAGE OUTLINES

“74HC/HCT/HCU/HCMOS Logic Package Outlines”

See

.

1997 Nov 25 4

Philips Semiconductors Product specification

Phase-locked-loop with VCO 74HC/HCT4046A

PIN DESCRIPTION

PIN NO. SYMBOL NAME AND FUNCTION

1 PCP
2 PC1
3 COMP
4 VCO

OUT

OUT

IN

OUT

5 INH inhibit input
6C1
7C1

A
B

8 GND ground (0 V)
9 VCO
10 DEM
11 R
12 R
13 PC2
14 SIG
15 PC3
16 V

IN

OUT
1
2

OUT

IN

OUT

CC

phase comparator pulse output
phase comparator 1 output
comparator input
VCO output

capacitor C1 connection A
capacitor C1 connection B

VCO input
demodulator output
resistor R1 connection
resistor R2 connection
phase comparator 2 output
signal input
phase comparator 3 output
positive supply voltage

Fig.1 Pin configuration. Fig.2 Logic symbol. Fig.3 IEC logic symbol.

1997 Nov 25 5

Philips Semiconductors Product specification

Phase-locked-loop with VCO 74HC/HCT4046A

C1

314476

CO OUT

DEM

R

S

COMP

VCO

OUTINH

IN

C1AC1

R

12

2

R2

R

11

1

R1

V

B

VCO

5109

SIG

IN

(a)

IN

4046A

PHASE

COMPARATOR

1

PHASE

COMPARATOR

2

PHASE

COMPARATOR

3

PC1

PC2
PCP

PC3

OUT

OUT 13
OUT

OUT 15

identical to 4046A

2

PHASE

COMPARATOR

1

R3

R4

C2

LOCK

DETECTOR

C

LD

C

CLD

7046A

PC2

OUTLD13

2

1

15

MGA847

(b)

(a) (b)

Fig.4 Functional diagram.

Fig.5 Logic diagram.

1997 Nov 25 6

Philips Semiconductors Product specification

Phase-locked-loop with VCO 74HC/HCT4046A

V

V

DEMOUT=VPC2OUT

=(φ

φ

DEMOUT

SIGIN−φCOMPIN

CC

=

---------- -

π

–()

φ

SIGINφCOMPIN

).

Fig.6 Phase comparator 1: average output voltage versus input phase difference.

Fig.7 Typical waveforms for PLL using phase comparator 1, loop locked at fo.

V

V

DEMOUT=VPC2OUT

=(φ

φ

DEMOUT

SIGIN

=

−φC

CC

---------- ­4π

OMPIN

).

–()

φ

SIGINφCOMPIN

Fig.8 Phase comparator 2: average output voltage versus input phase difference.

1997 Nov 25 7

Philips Semiconductors Product specification

Phase-locked-loop with VCO 74HC/HCT4046A

Fig.9 Typical waveforms for PLL using phase comparator 2, loop locked at fo.

V

DEMOUT=VPC3OUT

=(φ

φ

DEMOUT

SIGIN−φCOMPIN

V

CC

=

---------- ­2π

–()

φ

SIGINφCOMPIN

).

Fig.10 Phase comparator 3: average output voltage versus input phase difference:

Fig.11 Typical waveforms for PLL using phase comparator 3, loop locked at fo.

1997 Nov 25 8

Philips Semiconductors Product specification

Phase-locked-loop with VCO 74HC/HCT4046A

RECOMMENDED OPERATING CONDITIONS FOR 74HC/HCT

SYMBOL PARAMETER

74HC 74HCT

min. typ. max. min. typ. max.

V

CC

V

CC

DC supply voltage 3.0 5.0 6.0 4.5 5.0 5.5 V
DC supply voltage if VCO

2.0 5.0 6.0 4.5 5.0 5.5 V

section is not used

V

I

V

O

T

amb

DC input voltage range 0 V
DC output voltage range 0 V
operating ambient

−40 +85 −40 +85 °C see DC and AC

0V

CC

0V

CC

CC
CC

temperature range

T

amb

operating ambient

−40 +125 −40 +125 °C

temperature range

t

r,tf

input rise and fall times (pin 5) 6.0 1000 6.0 500 ns VCC= 2.0 V

6.0 500 6.0 500 ns V

6.0 400 6.0 500 ns V

RATINGS

Limiting values in accordance with the Absolute Maximum System (IEC 134)
Voltages are referenced to GND (ground = 0 V)

SYMBOL PARAMETER MIN. MAX. UNIT CONDITIONS

V

CC

±I

IK

±I

OK

±I

O

DC supply voltage −0.5 +7 V
DC input diode current 20 mA for VI<−0.5 V or VI> VCC+ 0.5 V
DC output diode current 20 mA for VO<−0.5 V or VO> VCC+ 0.5 V
DC output source or sink

25 mA for −0.5 V < VO< VCC+ 0.5 V

current

±I

; ±I

CC

T

stg

P

tot

DC VCCor GND current 50 mA

GND

storage temperature range −65 +150 °C
power dissipation per package

for temperature range: − 40 to +125 °C
74HC/HCT

plastic DIL 750 mW

above + 70 °C: derate linearly with 12 mW/K

plastic mini-pack (SO) 500 mW above + 70 °C: derate linearly with 8 mW/K

UNIT CONDITIONS

V
V

CHARACTERISTICS

= 4.5 V

CC

= 6.0 V

CC

1997 Nov 25 9

Philips Semiconductors Product specification

Phase-locked-loop with VCO 74HC/HCT4046A

DC CHARACTERISTICS FOR 74HC
Quiescent supply current

Voltages are referenced to GND (ground = 0 V)

SYMBOL PARAMETER

+25 −40 to +85 −40 to +125

min. typ. max. min. max. min. max.

quiescent supply

I

CC

current (VCO

8.0 80.0 160.0 µA 6.0

disabled)

Phase comparator section

Voltages are referenced to GND (ground = 0 V)

SYM­BOL

PARAMETER

+25 −40 to +85 −40 to +125

min. typ. max. min. max. min. max.

IH

DC coupled

V

HIGH level input voltage
SIGIN, COMP

V

IL

DC coupled

IN

LOW level input voltage
SIGIN, COMP

V

HIGH level output voltage

OH

PCP

OUT

,PC

IN

nOUT

1.5 1.2 1.5 1.5 V 2.0

3.15 2.4 3.15 3.15 4.5

4.2 3.2 4.2 4.2 6.0

0.8 0.5 0.5 0.5 V 2.0

2.1 1.35 1.35 1.35 4.5

2.8 1.8 1.8 1.8 6.0

1.9 2.0 1.9 1.9 V 2.0 V

4.4 4.5 4.4 4.4 4.5 −I

5.9 6.0 5.9 5.9 6.0 −I

V

V

HIGH level output voltage

OH

PCP

LOW level output voltage

OL

PCP

OUT

OUT

,PC

,PC

nOUT

nOUT

3.98 4.32 3.84 3.7 V 4.5 V

5.48 5.81 5.34 5.2 6.0 −I

0 0.1 0.1 0.1 V 2.0 V
0 0.1 0.1 0.1 4.5 I
0 0.1 0.1 0.1 6.0 I

V

±I

±I

LOW level output voltage

OL

PCP

input leakage current

I

OUT

,PC

SIGIN, COMP

3-state

OZ

nOUT

IN

0.15 0.26 0.33 0.4 V 4.5 V

0.16 0.26 0.33 0.4 6.0 I

OFF-state current
PC2

OUT

(°C)

T

amb

74HC V

UNIT

TEST CONDITIONS

CC

OTHER

(V)

pins 3, 5, and 14 at VCC;
pin 9 at GND; I
3 and 14 to be excluded

T

(°C)

amb

74HC V

UNIT

TEST CONDITIONS

CC

(V)

3.0 4.0 5.0 µA 2.0 V

7.0 9.0 11.0 3.0

18.0 23.0 27.0 4.5

30.0 38.0 45.0 6.0

0.5 5.0 10.0 µA 6.0 V

V

I

IH

or
V

IL

IH

or
V

IL
IH

or
V

IL

IH

or
V

IL
CC

or

GND

IH

or
V

IL

at pins

I

OTHER

−IO=20µA
=20µA

O

=20µA

O

−IO= 4.0 mA
= 5.2 mA

O

IO=20µA

=20µA

O

=20µA

O

IO= 4.0 mA

= 5.2 mA

O

VO=VCCor
GND

1997 Nov 25 10

Philips Semiconductors Product specification

Phase-locked-loop with VCO 74HC/HCT4046A

T

(°C)

amb

SYM­BOL

PARAMETER

+25 −40 to +85 −40 to +125

74HC V

UNIT

min. typ. max. min. max. min. max.

R

input resistance

I

SIGIN, COMP

IN

800 kΩ 3.0 V
250 kΩ 4.5
150 kΩ 6.0

VCO section

Voltages are referenced to GND (ground = 0 V)

T

(°C)

amb

SYM­BOL

PARAMETER

+25 −40 to +85 −40 to +125

74HC V

UNIT

min. typ. max. min. max. min. max.

V

V

V

V

V

V

V

±I

IH

IL

OH

OH

OL

OL

OL

I

HIGH level

input voltage
INH

LOW level

input voltage
INH

HIGH level

output voltage
VCO

OUT

HIGH level

output voltage
VCO

OUT

LOW level

output voltage
VCO

OUT

LOW level

output voltage
VCO

OUT

LOW level output

voltage C1A,C1

input leakage

2.1 1.7 2.1 2.1 V 3.0

3.15 2.4 3.15 3.15 4.5

4.2 3.2 4.2 4.2 6.0

1.3 0.9 0.9 0.9 V 3.0

2.1 1.35 1.35 1.35 4.5

2.8 1.8 1.8 1.8 6.0

2.9 3.0 2.9 2.9 V 3.0 V

4.4 4.5 4.4 4.4 4.5 −I

5.9 6.0 5.9 5.9 6.0 −I

3.98 4.32 3.84 3.7 V 4.5 V

5.48 5.81 5.34 5.2 6.0 −I

0 0.1 0.1 0.1 V 3.0 V
0 0.1 0.1 0.1 4.5 I
0 0.1 0.1 0.1 6.0 I

0.15 0.26 0.33 0.4 V 4.5 V

0.16 0.26 0.33 0.4 6.0 I

0.40 0.47 0.54 V 4.5 V

B

0.40 0.47 0.54 6.0 I

0.1 1.0 1.0 µA 6.0 V

current

INH, VCO

IN

R1 resistor range 3.0 300 kΩ 3.0 note 1

3.0 300 4.5

3.0 300 6.0

TEST CONDITIONS

CC

(V)

OTHER

V

I

at self-bias

I

operating point;
∆ V

= 0.5 V;

I

see Figs 12, 13
and 14

TEST CONDITIONS

CC

(V)

V

or
V

or
V

or
V

or
V

or
V

I

IH

IL

IH

IL
IH

IL

IH

IL
IH

IL
CC

OTHER

−IO=20µA

O
O

−IO= 4.0 mA

O

IO=20µA

O
O

IO= 4.0 mA

O

IO= 4.0 mA

O

or
GND

=20µA
=20µA

= 5.2 mA

=20µA
=20µA

= 5.2 mA

= 5.2 mA

1997 Nov 25 11