Philips 74hc hct4020 DATASHEETS

INTEGRATED CIRCUITS

DATA SH EET

For a complete data sheet, please also download:

•The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications

•The IC06 74HC/HCT/HCU/HCMOS Logic Package Information

•The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines

74HC/HCT4020

14-stage binary ripple counter

Product specification
File under Integrated Circuits, IC06

September 1993

Philips Semiconductors Product specification

14-stage binary ripple counter 74HC/HCT4020

FEATURES

• Output capability: standard

• ICC category: MSI

The 74HC/HCT4020 are 14-stage binary ripple counters
with a clock input (
master reset input (MR) and twelve fully buffered parallel
outputs (Q0, Q3to Q13).

The counter is advanced on the HIGH-to-LOW transition of

GENERAL DESCRIPTION

The 74HC/HCT4020 are high-speed Si-gate CMOS
devices and are pin compatible with the “4020” of the
“4000B” series. They are specified in compliance with
JEDEC standard no. 7A.

CP.
A HIGH on MR clears all counter stages and forces all

outputs LOW, independent of the state of CP.
Each counter stage is a static toggle flip-flop.

QUICK REFERENCE DATA

GND = 0 V; T

=25°C; tr=tf= 6 ns

amb

SYMBOL PARAMETER CONDITIONS

t

PHL/ tPLH

f

max

C

I

C

PD

propagation delay CL= 15 pF; VCC=5 V

CP to Q
Q
MR to Q

to Q

n

0

n+1

n

maximum clock frequency 101 52 MHz
input capacitance 3.5 3.5 pF
power dissipation capacitance per package notes 1 and 2 19 20 pF

CP), an overriding asynchronous

TYPICAL

UNIT

HC HCT

11 15 ns
66ns
17 19 ns

Notes

1. C

is used to determine the dynamic power dissipation (PD in µW):

PD

PD=CPD× V

2

× fi+ ∑ (CL× V

CC

2

× fo) where:

CC

fi= input frequency in MHz
fo= output frequency in MHz
∑ (CL× V

2

× fo) = sum of outputs

CC

CL= output load capacitance in pF
VCC= supply voltage in V

2. For HC the condition is VI= GND to V

CC

For HCT the condition is VI= GND to VCC− 1.5 V

ORDERING INFORMATION

“74HC/HCT/HCU/HCMOS Logic Package Information”

See

.

September 1993 2

Philips Semiconductors Product specification

14-stage binary ripple counter 74HC/HCT4020

PIN DESCRIPTION

PIN NO. SYMBOL NAME AND FUNCTION

9, 7, 5, 4, 6, 13, 12, 14, 15, 1, 2, 3 Q
8 GND ground (0 V)
10
11 MR master reset input (active HIGH)
16 V

, Q3to Q

0

13

parallel outputs

CP clock input (HIGH-to-LOW, edge-triggered)

CC

positive supply voltage

page

RCTR14

CT=0

CT

MGA829

9

0

7

3

5
4

6
13
12
14
15

1

2

3

13

Fig.1 Pin configuration. Fig.2 Logic symbol. Fig.3 IEC logic symbol.

September 1993 3