Philips 74hc hct4015 DATASHEETS

INTEGRATED CIRCUITS

DATA SH EET

For a complete data sheet, please also download:

•The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications

•The IC06 74HC/HCT/HCU/HCMOS Logic Package Information

•The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines

74HC/HCT4015

Dual 4-bit serial-in/parallel-out shift
register

Product specification
File under Integrated Circuits, IC06

December 1990

Philips Semiconductors Product specification

Dual 4-bit serial-in/parallel-out shift
register

FEATURES

• Output capability: standard

• ICC category: MSI

GENERAL DESCRIPTION

The 74HC/HCT4015 are high-speed Si-gate CMOS
devices and are pin compatible with the “4015” of the
“4000B” series. They are specified in compliance with
JEDEC standard no. 7A.

QUICK REFERENCE DATA

GND = 0 V; T

=25°C; tr=tf= 6 ns

amb

SYMBOL PARAMETER CONDITIONS

t

/ t

PHL

PLH

f

max

C

I

C

PD

propagation delay nCP to nQ

n

maximum clock frequency 110 74 MHz
input capacitance 3.5 3.5 pF
power dissipation capacitance per register notes 1 and 2 35 40 pF

The 74HC/HCT4015 are dual edge-triggered 4-bit static
shift registers (serial-to-parallel converters). Each shift
register has a serial data input (1D and 2D), a clock input
(1CP and 2CP), four fully buffered parallel outputs (1Q
1Q3 and 2Q0 to 2Q3) and an overriding asynchronous
master reset (1MR and 2MR). Information present on nD
is shifted to the first register position, and all data in the
register is shifted one position to the right on the
LOW-to-HIGH transition of nCP.
A HIGH on nMR clears the register and forces nQ0 to nQ
to LOW, independent of nCP and nD.

CL= 15 pF; VCC=5 V1618ns

74HC/HCT4015

TYPICAL

HC HCT

UNIT

to

0

3

Notes

1. C

is used to determine the dynamic power dissipation (PD in µW):

PD

PD=CPD× V

2

× fi+∑(CL× V

CC

2

× fo) where:

CC

fi= input frequency in MHz
fo= output frequency in MHz
∑ (CL× V

2

× fo) = sum of outputs

CC

CL= output load capacitance in pF
VCC= supply voltage in V

2. For HC the condition is VI= GND to V

CC

For HCT the condition is VI= GND to VCC− 1.5 V

ORDERING INFORMATION

“74HC/HCT/HCU/HCMOS Logic Package Information”

See

.

December 1990 2

Philips Semiconductors Product specification

Dual 4-bit serial-in/parallel-out shift register 74HC/HCT4015

PIN DESCRIPTION

PIN NO. SYMBOL NAME AND FUNCTION

5, 4, 3, 10 1Q
6, 14 1MR, 2MR asynchronous master reset inputs (active HIGH)
7, 15 1D, 2D serial data inputs
8 GND ground (0 V)
9, 1 1CP, 2CP clock inputs (LOW-to-HIGH, edge-triggered)
13, 12, 11, 2 2Q
16 V

0

0

CC

to 1Q

to 2Q

3

3

flip-flop outputs

flip-flop outputs
positive supply voltage

Fig.1 Pin configuration. Fig.2 Logic symbol. Fig.3 IEC logic symbol.

December 1990 3