Philips 74hc hct40102 DATASHEETS

INTEGRATED CIRCUITS

DATA SH EET

For a complete data sheet, please also download:

•The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications

•The IC06 74HC/HCT/HCU/HCMOS Logic Package Information

•The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines

74HC/HCT40102

8-bit synchronous BCD down
counter

Product specification
File under Integrated Circuits, IC06

December 1990

Philips Semiconductors Product specification

8-bit synchronous BCD down counter 74HC/HCT40102

FEATURES

• Cascadable

• Synchronous or asynchronous preset

• Output capability: standard

• ICCcategory: MSI

GENERAL DESCRIPTION

The 74HC/HCT40102 are high-speed Si-gate CMOS
devices and are pin compatible with the “40102” of the
“4000B” series. They are specified in compliance with
JEDEC standard no. 7A.

The 74HC/HCT40102 consist each of an 8-bit
synchronous down counter with a single output which is
active when the internal count is zero. The “40102” is
configured as two cascaded 4-bit BCD counters and has
control inputs for enabling or disabling the clock (CP), for
clearing the counter to its maximum count, and for
presetting the counter either synchronously or
asynchronously. All control inputs and the terminal count
output (

TC) are active-LOW logic.

In normal operation, the counter is decremented by one
count on each positive-going transition of the clock (CP).
Counting is inhibited when the terminal enable input (TE)
is HIGH. The terminal count output (TC) goes LOW when
the count reaches zero ifTE is LOW, and remains LOW for
one full clock period.

When the synchronous preset enable input (PE) is LOW,
data at the jam input (P0to P7) is clocked into the counter
on the next positive-going clock transition regardless of the
state of TE. When the asynchronous preset enable input
(PL) is LOW, data at the jam input (P0to P7) is
asynchronously forced into the counter regardless of the
state of PE, TE, or CP. The jam inputs (P0to P7) represent
two 4-bit BCD words.

When the master reset input (MR) is LOW, the counter is
asynchronously cleared to its maximum count (decimal

99) regardless of the state of any other input. The
precedence relationship between control inputs is
indicated in the function table.

If all control inputs except TE are HIGH at the time of zero
count, the counters will jump to the maximum count, giving
a counting sequence of 100 clock pulses long.
The “40102” may be cascaded using the TE input and the
TC output, in either a synchronous or ripple mode.

APPLICATIONS

• Divide-by-n counters

• Programmable timers

• Interrupt timers

• Cycle/program counters

QUICK REFERENCE DATA

GND = 0 V; T

=25°C; tr=tf= 6 ns

amb

SYMBOL PARAMETER CONDITIONS

t

PHL

f

max

C
C

I
PD

/ t

PLH

propagation delay CP to TC CL= 15 pF; VCC= 5 V 30 31 ns
maximum clock frequency 30 30 MHz
input capacitance 3.5 3.5 pF
power dissipation capacitance per package notes 1 and 2 20 25 pF

Notes

1. C

is used to determine the dynamic power dissipation (PDin µW):

PD

PD=CPD× V

2

× fi+∑(CL× V

CC

2

× fo) where:

CC

fi= input frequency in MHz
fo= output frequency in MHz
∑ (CL× V

2

× fo) = sum of outputs

CC

CL= output load capacitance in pF
VCC= supply voltage in V

December 1990 2

TYPICAL

UNIT

HC HCT

Philips Semiconductors Product specification

8-bit synchronous BCD down counter 74HC/HCT40102

2. For HC the condition is VI= GND to V

CC

For HCT the condition is VI= GND to VCC− 1.5 V

ORDERING INFORMATION

“74HC/HCT/HCU/HCMOS Logic Package Information”

See

.

PIN DESCRIPTION

PIN NO. SYMBOL NAME AND FUNCTION

1 CP clock input (LOW-to-HIGH, edge-triggered)
2
3
4, 5, 6, 7, 10, 11, 12, 13 P

MR asynchronous master reset input (active LOW)
TE terminal enable input

0

to P

7

jam inputs
8 GND ground (0 V)
9
14
15
16 V

PL asynchronous preset enable input (active LOW)
TC terminal count output (active LOW)
PE synchronous preset enable input (active LOW)

CC

positive supply voltage

Fig.1 Pin configuration. Fig.2 Logic symbol. Fig.3 IEC logic symbol.

December 1990 3

Philips Semiconductors Product specification

8-bit synchronous BCD down counter 74HC/HCT40102

Fig.4 Functional diagram.

FUNCTION TABLE

CONTROL INPUTS

MR PL PE TE

HHHH
H H H L count down
H H L X preset on next LOW-to HIGH clock transition
HLXX

L X X X clear to maximum count

Notes

1. Clock connected to CP.

2. Synchronous operation: changes occur on the LOW-to-HIGH CP transition.

3. Jam inputs: MSD = P

H = HIGH voltage level
L = LOW voltage level
X = don’t care

, LSD = P0.

7

PRESET MODE ACTION

inhibit counter

synchronous

asynchronous

preset asynchronously

December 1990 4