Philips 74hc hct393 DATASHEETS

INTEGRATED CIRCUITS

DATA SH EET

For a complete data sheet, please also download:

•The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications

•The IC06 74HC/HCT/HCU/HCMOS Logic Package Information

•The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines

74HC/HCT393

Dual 4-bit binary ripple counter

Product specification
File under Integrated Circuits, IC06

December 1990

Philips Semiconductors Product specification

Dual 4-bit binary ripple counter 74HC/HCT393

FEATURES

• Two 4-bit binary counters with individual clocks

• Divide-by any binary module up to 28 in one package

• Two master resets to clear each 4-bit counter

individually

• Output capability: standard

• ICC category: MSI

The 74HC/HCT393 are 4-bit binary ripple counters with
separate clocks (1
and 2MR) inputs to each counter. The operation of each
half of the “393” is the same as the “93” except no external
clock connections are required.
The counters are triggered by a HIGH-to-LOW transition of
the clock inputs. The counter outputs are internally
connected to provide clock inputs to succeeding stages.
The outputs of the ripple counter do not change
synchronously and should not be used for high-speed

GENERAL DESCRIPTION

The 74HC/HCT393 are high-speed Si-gate CMOS devices
and are pin compatible with low power Schottky TTL
(LSTTL). They are specified in compliance with JEDEC
standard no. 7A.

address decoding.
The master resets are active-HIGH asynchronous inputs

to each 4-bit counter identified by the “1” and “2” in the pin
description.
A HIGH level on the nMR input overrides the clock and
sets the outputs LOW.

QUICK REFERENCE DATA

GND = 0 V; T

= 25 °C; tr= tf= 6 ns

amb

SYMBOL PARAMETER CONDITIONS

t

PHL

f

max

C
C

I
PD

/ t

PLH

propagation delay CL= 15 pF; VCC= 5 V
n

CP to nQ
nQ to nQ
nMR to nQ

0

n+1

n

maximum clock frequency 99 53 MHz
input capacitance 3.5 3.5 pF
power dissipation capacitance per counter notes 1 and 2 23 25 pF

CP and 2 CP) and master reset (1MR

TYPICAL

UNIT

HC HCT

12 20 ns
56ns
11 15 ns

Notes

1. C

is used to determine the dynamic power dissipation (PDin µW):

PD

PD= CPD× V

2

× fi+∑(CL× V

CC

2

× fo) where:

CC

fi= input frequency in MHz
fo= output frequency in MHz
∑ (CL× V

2

× fo) = sum of outputs

CC

CL= output load capacitance in pF
VCC= supply voltage in V

2. For HC the condition is VI= GND to V

CC

For HCT the condition is VI= GND to VCC− 1.5 V

ORDERING INFORMATION

“74HC/HCT/HCU/HCMOS Logic Package Information”

See

December 1990 2

.

Philips Semiconductors Product specification

Dual 4-bit binary ripple counter 74HC/HCT393

PIN DESCRIPTION

PIN NO. SYMBOL NAME AND FUNCTION

1, 13 1
2, 12 1MR, 2MR asynchronous master reset inputs (active HIGH)
3, 4, 5, 6, 11, 10, 9, 8 1Q
7 GND ground (0 V)
14 V

CP, 2CP clock inputs (HIGH-to-LOW, edge-triggered)

to 1Q3, 2Q0to 2Q

0

CC

3

flip-flop outputs

positive supply voltage

Fig.1 Pin configuration. Fig.2 Logic symbol. Fig.3 IEC logic symbol.

December 1990 3