Philips 74hc hct366 DATASHEETS

INTEGRATED CIRCUITS

DATA SH EET

For a complete data sheet, please also download:

•The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications

•The IC06 74HC/HCT/HCU/HCMOS Logic Package Information

•The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines

74HC/HCT366

Hex buffer/line driver; 3-state;
inverting

Product specification
File under Integrated Circuits, IC06

December 1990

Philips Semiconductors Product specification

Hex buffer/line driver; 3-state; inverting 74HC/HCT366

FEATURES

• Inverting outputs

• Output capability: bus driver

• ICC category: MSI

The 74HC/HCT366 are hex inverting buffer/line drivers
with 3-state outputs. The 3-state outputs (nY) are
controlled by the output enable inputs (

A HIGH on OEncauses the outputs to assume a high
impedance OFF-state.

The ”366” is identical to the “365” but has inverting outputs.

GENERAL DESCRIPTION

The 74HC/HCT366 are high-speed Si-gate CMOS devices
and are pin compatible with low power Schottky TTL
(LSTTL). They are specified in compliance with JEDEC
standard no. 7A.

QUICK REFERENCE DATA

GND = 0 V; T

= 25 °C; tr= tf= 6 ns

amb

SYMBOL PARAMETER CONDITIONS

t

PHL

/ t

PLH

propagation delay

CL= 15 pF; VCC= 5 V 10 11 ns

nA to nY

C

I

C

PD

input capacitance 3.5 3.5 pF
power dissipation capacitance per buffer notes 1 and 2 30 30 pF

Notes

1. C

is used to determine the dynamic power dissipation (PDin µW):

PD

PD= CPD× V

2

× fi+∑(CL× V

CC

2

× fo) where:

CC

fi= input frequency in MHz
fo= output frequency in MHz
∑ (CL× V

2

× fo) = sum of outputs

CC

CL= output load capacitance in pF
VCC= supply voltage in V

2. For HC the condition is VI= GND to V

CC

For HCT the condition is VI= GND to VCC− 1.5 V

OE1, OE2).

TYPICAL

UNIT

HC HCT

ORDERING INFORMATION

See

“74HC/HCT/HCU/HCMOS Logic Package Information”

December 1990 2

.

Philips Semiconductors Product specification

Hex buffer/line driver; 3-state; inverting 74HC/HCT366

PIN DESCRIPTION

PIN NO. SYMBOL NAME AND FUNCTION

1, 15
2, 4, 6, 10, 12, 14 1A to 6A data inputs
3, 5, 7, 9, 11, 13 1
8 GND ground (0 V)
16 V

OE1, OE

2

output enable inputs (active LOW)

Y to 6Y data outputs

CC

positive supply voltage

Fig.1 Pin configuration. Fig.2 Logic symbol. Fig.3 IEC logic symbol.

December 1990 3