Philips 74hc hct280 DATASHEETS

INTEGRATED CIRCUITS

DATA SH EET

For a complete data sheet, please also download:

•The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications

•The IC06 74HC/HCT/HCU/HCMOS Logic Package Information

•The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines

74HC/HCT280

9-bit odd/even parity
generator/checker

Product specification
File under Integrated Circuits, IC06

December 1990

Philips Semiconductors Product specification

9-bit odd/even parity generator/checker 74HC/HCT280

FEATURES

• Word-length easily expanded by cascading

• Similar pin configuration to the “180” for easy system

up-grading

• Generates either odd or even parity for nine data bits

• Output capability: standard

• ICC category: MSI

transmission or data retrieval systems. Both even and odd
parity outputs are available for generating or checking
even or odd parity up to 9 bits.

The even parity output (∑
of data inputs (I0 to I8) are HIGH. The odd parity output (∑0)
is HIGH when an odd number of data inputs are HIGH.

Expansion to larger word sizes is accomplished by tying
the even outputs (∑E) of up to nine parallel devices to the
data inputs of the final stage. For a single-chip 16-bit

GENERAL DESCRIPTION

even/odd parity generator/checker, see
PC74HC/HCT7080.

The 74HC/HCT280 are high-speed Si-gate CMOS devices
and are pin compatible with low power Schottky TTL
(LSTTL). They are specified in compliance with JEDEC
standard no. 7A.

The 74HC/HCT280 are 9-bit parity generators or checkers

APPLICATIONS

• 25-line parity generator/checker

• 81-line parity generator/checker

commonly used to detect errors in high-speed data

QUICK REFERENCE DATA

GND = 0 V; T

=25°C; tr=tf= 6 ns

amb

SYMBOL PARAMETER CONDITIONS

t

PHL

C
C

/ t

I
PD

propagation delay CL= 15 pF; VCC=5 V

PLH

I

to ∑

n

E

I

to ∑

n

O

input capacitance 3.5 3.5 pF
power dissipationcapacitance per package notes 1 and 2 65 65 pF

) is HIGH when an even number

E

TYPICAL

UNIT

HC HCT

17 18 ns
20 22 ns

Notes

1. C

is used to determine the dynamic power dissipation (PD in µW):

PD

PD=CPD× V

2

× fi+∑(CL× V

CC

2

× fo) where:

CC

fi= input frequency in MHz
fo= output frequency in MHz
∑ (CL× V

2

× fo) = sum of outputs

CC

CL= output load capacitance in pF
VCC= supply voltage in V

2. For HC the condition is VI= GND to V

CC

For HCT the condition is VI= GND to VCC− 1.5 V

ORDERING INFORMATION

“74HC/HCT/HCU/HCMOS Logic Package Information”

See

December 1990 2

.

Philips Semiconductors Product specification

9-bit odd/even parity generator/checker 74HC/HCT280

PIN DESCRIPTION

PIN NO. SYMBOL NAME AND FUNCTION

8, 9, 10, 11, 12, 13, 1, 2, 4 I
5, 6 ∑
7 GND ground (0 V)
14 V

to I

0

E

CC

, ∑

8

O

data inputs
parity outputs

positive supply voltage

Fig.1 Pin configuration. Fig.2 Logic symbol. Fig.3 IEC logic symbol.

December 1990 3