Philips 74hc hct273 DATASHEETS

INTEGRATED CIRCUITS

DATA SH EET

For a complete data sheet, please also download:

•The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications

•The IC06 74HC/HCT/HCU/HCMOS Logic Package Information

•The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines

74HC/HCT273

Octal D-type flip-flop with reset;
positive-edge trigger

Product specification
File under Integrated Circuits, IC06

September 1993

Philips Semiconductors Product specification

Octal D-type flip-flop with reset;
positive-edge trigger

FEATURES

• Ideal buffer for MOS microprocessor or memory

• Common clock and master reset

• Eight positive edge-triggered D-type flip-flops

• See “377” for clock enable version

• See “373” for transparent latch version

• See “374” for 3-state version

• Output capability; standard

• ICC category: MSI

74HC/HCT273

GENERAL DESCRIPTION

The 74HC/HCT273 are high-speed Si-gate CMOS devices
and are pin compatible with low power Schottky TTL
(LSTTL). They are specified in compliance with JEDEC
standard no. 7A.

The 74HC/HCT273 have eight edge-triggered, D-type
flip-flops with individual D inputs and Q outputs. The
common clock (CP) and master reset (MR) inputs load and
reset (clear) all flip-flops simultaneously.
The state of each D input, one set-up time before the
LOW-to-HIGH clock transition, is transferred to the
corresponding output (Qn) of the flip-flop.

All outputs will be forced LOW independently of clock or
data inputs by a LOW voltage level on the MR input.

The device is useful for applications where the true output
only is required and the clock and master reset are
common to all storage elements.

QUICK REFERENCE DATA

GND = 0 V; T

=25°C; tr=tf= 6 ns

amb

SYMBOL PARAMETER CONDITIONS

t

PHL/ tPLH

f

max

C

I

C

PD

propagation delay CL= 15 pF; VCC=5 V

CP to Q
MR to Q

n

n

maximum clock frequency 66 36 MHz
input capacitance 3.5 3.5 pF
power dissipation capacitance per flip-flop notes 1 and 2 20 23 pF

Notes

1. C

is used to determine the dynamic power dissipation (PD in µW):

PD

PD=CPD× V

2

× fi+ ∑ (CL× V

CC

2

× fo) where:

CC

fi= input frequency in MHz
fo= output frequency in MHz
∑ (CL× V

2

× fo) = sum of outputs

CC

CL= output load capacitance in pF
VCC= supply voltage in V

2. For HC the condition is VI= GND to V

CC

For HCT the condition is VI= GND to VCC− 1.5 V

TYPICAL

UNIT

HC HCT

15 15 ns
15 20 ns

ORDERING INFORMATION

“74HC/HCT/HCU/HCMOS Logic Package Information”

See

September 1993 2

.

Philips Semiconductors Product specification

Octal D-type flip-flop with reset;

74HC/HCT273

positive-edge trigger

PIN DESCRIPTION

PIN NO. SYMBOL NAME AND FUNCTION

1
2, 5, 6, 9, 12, 15, 16, 19 Q
3, 4, 7, 8, 13, 14, 17, 18 D
10 GND ground (0 V)
11 CP clock input (LOW-to-HIGH, edge-triggered)
20 V

MR master reset input (active LOW)

to Q

0

to D

0

CC

7

7

flip-flop outputs
data inputs

positive supply voltage

Fig.1 Pin configuration. Fig.2 Logic symbol. Fig.3 IEC logic symbol.

September 1993 3