Philips 74HC,HCT244 Datasheet

DATA SH EET

Product specification
File under Integrated Circuits, IC06

December 1990

INTEGRATED CIRCUITS

74HC/HCT244

Octal buffer/line driver; 3-state

For a complete data sheet, please also download:

•The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications

•The IC06 74HC/HCT/HCU/HCMOS Logic Package Information

•The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines

December 1990 2

Philips Semiconductors Product specification

Octal buffer/line driver; 3-state 74HC/HCT244

FEATURES

• Output capability: bus driver

• ICC category: MSI

GENERAL DESCRIPTION

The 74HC/HCT244 are high-speed Si-gate CMOS devices
and are pin compatible with low power Schottky TTL
(LSTTL). They are specified in compliance with JEDEC
standard no. 7A.

The 74HC/HCT244 are octal non-inverting buffer/line
drivers with 3-state outputs. The 3-state outputs are
controlled by the output enable inputs 1

OE and 2OE.
A HIGH on nOE causes the outputs to assume a high
impedance OFF-state. The “244” is identical to the “240”
but has non-inverting outputs.

QUICK REFERENCE DATA

GND = 0 V; T

amb

=25°C; tr=tf= 6 ns

Notes

1. C

PD

is used to determine the dynamic power dissipation (PD in µW):

PD=CPD× V

CC

2

× fi+∑ (CL× V

CC

2

× fo) where:
fi= input frequency in MHz
fo= output frequency in MHz
∑ (CL× V

CC

2

× fo) = sum of outputs
CL= output load capacitance in pF
VCC= supply voltage in V

2. For HC the condition is VI= GND to V

CC

For HCT the condition is VI= GND to VCC− 1.5 V

ORDERING INFORMATION

See

“74HC/HCT/HCU/HCMOS Logic Package Information”

.

SYMBOL PARAMETER CONDITIONS

TYPICAL

UNIT

HC HCT

t

PHL

/ t

PLH

propagation delay

1An to 1Yn;
2An to 2Y

n

CL= 15 pF; VCC=5V 9 11 ns

C

I

input capacitance 3.5 3.5 pF

C

PD

power dissipation capacitance per buffer notes 1 and 2 35 35 pF

December 1990 3

Philips Semiconductors Product specification

Octal buffer/line driver; 3-state 74HC/HCT244

PIN DESCRIPTION

PIN NO. SYMBOL NAME AND FUNCTION

11

OE output enable input (active LOW)

2, 4, 6, 8 1A

0

to 1A

3

data inputs

3, 5, 7, 9 2Y

0

to 2Y

3

bus outputs
10 GND ground (0 V)
17, 15, 13, 11 2A

0

to 2A

3

data inputs
18, 16, 14, 12 1Y

0

to 1Y

3

bus outputs
19 2

OE output enable input (active LOW)

20 V

CC

positive supply voltage

Fig.1 Pin configuration. Fig.2 Logic symbol. Fig.3 IEC logic symbol.