Philips 74hc hct242 DATASHEETS

INTEGRATED CIRCUITS
DATA SH EET
The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications
The IC06 74HC/HCT/HCU/HCMOS Logic Package Information
The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines
74HC/HCT242
Quad bus transceiver; 3-state; inverting
Product specification File under Integrated Circuits, IC06
December 1990
Philips Semiconductors Product specification
Quad bus transceiver; 3-state; inverting 74HC/HCT242

FEATURES

Inverting 3-state outputs
2-way asynchronous data bus communication
Output capability: bus driver
ICC category: MSI
(LSTTL). They are specified in compliance with JEDEC standard no. 7A.
The 74HC/HCT242 are quad bus transceivers featuring inverting 3-state bus compatible outputs in both send and receive directions. They are designed for 4-line asynchronous 2-way data communications between data buses.

GENERAL DESCRIPTION

The 74HC/HCT242 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL
The output enable inputs ( isolate the buses.
The “242” is similar to the “243” but has inverting outputs.

QUICK REFERENCE DATA

GND = 0 V; T
= 25 °C; tr= tf= 6 ns
amb
SYMBOL PARAMETER CONDITIONS
t
PHL
/ t
PLH
propagation delay
CL= 15 pF; VCC= 5 V 7 10 ns Anto Bn; Bnto A
n
C
I
C
I/O
C
PD
input capacitance 3.5 3.5 pF input/output capacitance 10 10 pF power dissipation capacitance per transceiver notes 1 and 2 29 32 pF
OEAand OEB) can be used to
TYPICAL
UNIT
HC HCT
Notes
1. C
is used to determine the dynamic power dissipation (PDin µW):
PD
PD= CPD× V
2
× fi+∑(CV
CC
2
× fo) where:
CC
fi= input frequency in MHz fo= output frequency in MHz (CV
2
× fo) = sum of outputs
CC
CL= output load capacitance in pF VCC= supply voltage in V
2. For HC the condition is VI= GND to V
CC
For HCT the condition is VI= GND to VCC− 1.5 V

ORDERING INFORMATION

“74HC/HCT/HCU/HCMOS Logic Package Information”
See
.
December 1990 2
Philips Semiconductors Product specification
Quad bus transceiver; 3-state; inverting 74HC/HCT242

PIN DESCRIPTION

PIN NO. SYMBOL NAME AND FUNCTION
1 2, 12 n.c. not connected 3, 4, 5, 6 A 7 GND ground (0 V) 11, 10, 9, 8 B 13 OE 14 V
OE
0
0
CC
A
to A
to B
B
output enable input (active LOW)
3
3
data inputs/outputs
data inputs/outputs output enable input positive supply voltage
Fig.1 Pin configuration. Fig.2 Logic symbol. Fig.3 IEC logic symbol.
December 1990 3
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