Philips 74hc hct240 DATASHEETS
INTEGRATED CIRCUITS
DATA SH EET
For a complete data sheet, please also download:
•The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications
•The IC06 74HC/HCT/HCU/HCMOS Logic Package Information
•The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines
74HC/HCT240
Octal buffer/line driver; 3-state;
inverting
Product specification
File under Integrated Circuits, IC06
December 1990
Philips Semiconductors Product specification
Octal buffer/line driver; 3-state;
inverting
FEATURES
• Output capability: bus driver
• ICC category: MSI
QUICK REFERENCE DATA
GND = 0 V; T
=25°C; tr=tf= 6 ns
amb
SYMBOL PARAMETER CONDITIONS
t
PHL/ tPLH
propagation delay
1An to 1Yn;
C
I
C
PD
2An to 2Y
input capacitance 3.5 3.5 pF
power dissipation capacitance per buffer notes 1 and 2 30 30 pF
n
GENERAL DESCRIPTION
The 74HC/HCT240 are high-speed Si-gate CMOS devices
and are pin compatible with low power Schottky TTL
(LSTTL). They are specified in compliance with JEDEC
standard no. 7A.
The 74HC/HCT240 are octal inverting buffer/line drivers
with 3-state outputs. The 3-state outputs are controlled by
the output enable inputs 1OE and 2OE. A HIGH on nOE
causes the outputs to assume a high impedance
OFF-state. The “240” is identical to the “244” but has
inverting outputs.
CL= 15 pF; VCC=5 V99ns
74HC/HCT240
TYPICAL
UNIT
HC HCT
Notes
1. C
is used to determine the dynamic power dissipation (PD in µW):
PD
PD=CPD× V
2
× fi+ ∑ (CL× V
CC
2
× fo) where:
CC
fi= input frequency in MHz
fo= output frequency in MHz
∑ (CL× V
2
× fo) = sum of outputs
CC
CL= output load capacitance in pF
VCC= supply voltage in V
2. For HC the condition is VI= GND to V
CC
For HCT the condition is VI= GND to VCC− 1.5 V
ORDERING INFORMATION
“74HC/HCT/HCU/HCMOS Logic Package Information”
See
.
December 1990 2
Philips Semiconductors Product specification
Octal buffer/line driver; 3-state; inverting 74HC/HCT240
PIN DESCRIPTION
PIN NO. SYMBOL NAME AND FUNCTION
11
2, 4, 6, 8 1A
3, 5, 7, 9 2Y
10 GND ground (0 V)
17, 15, 13, 11 2A
18, 16, 14, 12 1Y
19 2
20 V
OE output enable input (active LOW)
to 1A
0
to 2Y
0
to 2A
0
to 1Y
0
3
3
3
3
data inputs
bus outputs
data inputs
bus outputs
OE output enable input (active LOW)
CC
positive supply voltage
Fig.1 Pin configuration. Fig.2 Logic symbol. Fig.3 IEC logic symbol.
December 1990 3
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