Philips 74hc hct192 DATASHEETS

INTEGRATED CIRCUITS

DATA SH EET

For a complete data sheet, please also download:

•The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications

•The IC06 74HC/HCT/HCU/HCMOS Logic Package Information

•The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines

74HC/HCT192

Presettable synchronous BCD
decade up/down counter

Product specification
File under Integrated Circuits, IC06

December 1990

Philips Semiconductors Product specification

Presettable synchronous BCD decade
up/down counter

FEATURES

• Synchronous reversible counting

• Asynchronous parallel load

• Asynchronous reset

• Expandable without external logic

• Output capability: standard

• ICC category: MSI

GENERAL DESCRIPTION

The 74HC/HCT192 are high-speed Si-gate CMOS devices
and are pin compatible with low power Schottky TTL
(LSTTL). They are specified in compliance with JEDEC
standard no. 7A.

The 74HC/HCT192 are synchronous BCD up/down
counters. Separate up/down clocks, CP
respectively, simplify operation. The outputs change state
synchronously with the LOW-to-HIGH transition of either
clock input. If the CPU clock is pulsed while CPD is held
HIGH, the device will count up. If the CPD clock is pulsed
while CPU is held HIGH, the device will count down. Only
one clock input can be held HIGH at any time, or
erroneous operation will result. The device can be cleared
at any time by the asynchronous master reset input (MR);
it may also be loaded in parallel by activating the
asynchronous parallel load input (PL).

The “192” contains four master-slave JK flip-flops with the
necessary steering logic to provide the asynchronous
reset, load, and synchronous count up and count down
functions.

Each flip-flop contains JK feedback from slave to master,
such that a LOW-to-HIGH transition on the CPD input will
decrease the count by one, while a similar transition on the
CPU input will advance the count by one.

and CP

U

D

74HC/HCT192

One clock should be held HIGH while counting with the
other, otherwise the circuit will either count by two’s or not
at all, depending on the state of the first flip-flop, which
cannot toggle as long as either clock input is LOW.
Applications requiring reversible operation must make the
reversing decision while the activating clock is HIGH to
avoid erroneous counts.

The terminal count up (TCU) and terminal count down
(TCD) outputs are normally HIGH. When the circuit has
reached the maximum count state of 9, the next
HIGH-to-LOW transition of CPU will causeTCU to go LOW.
TCU will stay LOW until CPU goes HIGH again, duplicating
the count up clock.

Likewise, the TCD output will go LOW when the circuit is in
the zero state and the CPD goes LOW. The terminal count
outputs can be used as the clock input signals to the next
higher order circuit in a multistage counter, since they
duplicate the clock waveforms. Multistage counters will not
be fully synchronous, since there is a slight delay time
difference added for each stage that is added.

The counter may be preset by the asynchronous parallel
load capability of the circuit. Information present on the
parallel data inputs (D0 to D3) is loaded into the counter
and appears on the outputs (Q0 to Q3) regardless of the
conditions of the clock inputs when the parallel load (PL)
input is LOW. A HIGH level on the master reset (MR) input
will disable the parallel load gates, override both clock
inputs and set all outputs (Q0 to Q3) LOW. If one of the
clock inputs is LOW during and after a reset or load
operation, the next LOW-to-HIGH transition of that clock
will be interpreted as a legitimate signal and will be
counted.

December 1990 2

Philips Semiconductors Product specification

Presettable synchronous BCD decade
up/down counter

QUICK REFERENCE DATA

GND = 0 V; T

SYMBOL PARAMETER CONDITIONS

t

/ t

PHL

PLH

f

max

C

I

C

PD

Notes

1. C

is used to determine the dynamic power dissipation (PD in µW):

PD

PD=CPD× V
fi= input frequency in MHz
fo= output frequency in MHz
∑ (CL× V
CL= output load capacitance in pF
VCC= supply voltage in V

2. For HC the condition is VI= GND to V
For HCT the condition is VI= GND to VCC−1.5 V

=25°C; tr=tf= 6 ns

amb

propagation delay CPD, CPU to Q
maximum clock frequency 40 45 MHz

n

CL= 15 pF; VCC=5V

input capacitance 3.5 3.5 pF
power dissipation capacitance per package notes 1 and 2 24 28 pF

2

× fi+∑ (CL× V

CC

2

× fo) = sum of outputs

CC

2

× fo) where:

CC

CC

74HC/HCT192

TYPICAL

UNIT

HC HCT

20 20 ns

ORDERING INFORMATION

“74HC/HCT/HCU/HCMOS Logic Package Information”

See

.

December 1990 3

Philips Semiconductors Product specification

Presettable synchronous BCD decade
up/down counter

PIN DESCRIPTION

PIN NO. SYMBOL NAME AND FUNCTION

3, 2, 6, 7 Q
4CP
5CP
8 GND ground (0 V)
11
12
13
14 MR asynchronous master reset input (active HIGH)
15, 1, 10, 9 D
16 V

Note

1. LOW-to-HIGH, edge triggered

to Q

0

3
D
U

flip-flop outputs
count down clock input
count up clock input

(1)

(1)

PL asynchronous parallel load input (active LOW)
TC
TC

U
D

to D

0

CC

3

terminal count up (carry) output (active LOW)
terminal count down (borrow) output (active LOW)

data inputs
positive supply voltage

74HC/HCT192

Fig.1 Pin configuration. Fig.2 Logic symbol. Fig.3 IEC logic symbol.

December 1990 4